Simple explaination based on truth table:
While PL is low, anything that happens on the CP, CE and DS pins is ignored, levels on pins D0-D6 are saved into the internal shift registers, and D7 is saved into the shift register and output on Q7. So PL has to be low at some point in order to load the levels from the D0-D7 pins into the registers
When PL transitions from low to high, the last levels on D0-D7 are latched into the shift registers.
While PL is high, The CP, CE and DS pins start working and anything that happens on the D0-D7 pins is ignored. As long as the CE pin is low, clock pulses on the CP pin will serially shift data though the registers, and then out of the part on the Q7 and (Q7not) pins. The DS pin feeds into the first register and can be used to connect multiple HC165 parts together in a longer chain.
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