confusion with the CD74HC165 8 bit register

[falingtrea]

putting the PL low .. something like that ??

I would do this (and make sure the CE pin is pulled low always) :

TRISE = %11111100 	' Set PORTE to all input
            
Clock   var PORTE.0   'CP
Load    var PORTE.1   'PL
Data_1  var PORTE.2  'Q7  out
input1 var byte

low Load
             
Mainloop:

  high Load
  shiftin Data_1,Clock,0,[input1 \8]
  low Load

  lcdout $FE,1, "Shift in"
  lcdout $FE,$C0, dec2 input1
  pause 300
			
GOTO Mainloop
End