confusion with the CD74HC165 8 bit register

[lerameur]

I think I have things cleared up. Data is Q7, Clock=CP, Pulse=PL (send a signal to receive the byte with shiftin command) and CE is grounded. ?!?

[HenrikOlsson]

Hi,
Yes, PL is parallel load - a logic low level on this input is what loads the shiftregister with the 8 databits. This way you know that all bits you shift in is from the "same moment in time". The Shiftin command does not handle this pin for you, you need to pulse it "manualy".

Correct, Q7 is the serial output of the shiftregister.

CE is chip enable or clock enable if you like, pull it low to use the CP pin as a positive clock input or tie the CP high and use the CE pin as a negative clock input.

Note that the '165 does not "send" the data out when you pulse the PL pin. It is the Shiftin command that "pulls" the data out of the shiftregsiter. Shiftin generates the clock pulses the '165 uses to shift the databits thru the shiftregister.

[falingtrea]

Also the PL (parallel load) signal needs to be High in order to clock data out of the serial data pin, but also needs to go low in order to sample the data on the parallel pins. Simplest thing to do is to invert the CE signal and use that to control the PL signal. That is how I turned the HC165 into a simple SPI-like interface (Clock, Data out, and Chip Enable).

[lerameur]

Ok, I understand pretty much how the chip works, it was the bridge between how Picbasic language treat the shiftin code that was troubling me.

Ok I have this code on a Pic16F887, I am only getting '00' as my output, I tried switcing ports ( CP and PL just to see, but no luck). My parallel input have random 0 and 5v for try out.

'@ __config _CONFIG1, _INTRC_OSC_NOCLKOUT & _WDT_ON & _MCLRE_OFF & _LVP_OFF & _CP_OFF
OSCCON = %01110000 '8 Mhz
DEFINE OSC 8
ANSELH = 0


'/////////////////////////
'// LCD configuration //
'/////////////////////////

DEFINE LCD_DREG PORTB 	' Set LCD Data port
DEFINE LCD_DBIT 4 		' Set starting Data bit (0 or 4) if 4-bit bus  RB.4, RB.5, RB.6, RB.7
DEFINE LCD_RSREG PORTB 	' Set LCD Register Select port
DEFINE LCD_RSBIT 1 		' Set LCD Register Select bit
DEFINE LCD_EREG PORTB	' Set LCD Enable port
DEFINE LCD_EBIT 0 		' Set LCD Enable bit
DEFINE LCD_BITS 4 		' Set LCD bus size (4 or 8 bits) '4 therefore put wire at 4, 5, 6 and 7 of LCD
DEFINE LCD_LINES 2 		' Set number of lines on LCD
DEFINE LCD_COMMANDUS 2500
DEFINE LCD_DATAUS 250
DEFINE CHAR_PACING 2000
pause 500



TRISE = %11111100 	' Set PORTE to all input
            
Clock   var PORTE.0   'CP
Load    var PORTE.1   'PL
Data_1  var PORTE.2  'Q7  out
input1 var byte
             
Mainloop:

pulsout Load,1
shiftin Data_1,Clock,0,[input1 \8]
	lcdout $FE,1, "Shift in"
	lcdout $FE,$C0, dec2 input1
	pause 300
	
	
			
GOTO Mainloop
End

[mackrackit]

It has been a couple of versions of PBP since I have used a shiftin register, but I remember
something about the MODE numbers not working. I know, it should not make a difference.
Just for giggles try.

include "modedefs.bas"
'
'
'
shiftin Data_1,Clock,MSBPre,.....

[HenrikOlsson]

Hi,
Like Tim said, the PL needs to idle high in order to shift the data out. To load the 8 bits into the register you pulse it low - you're currently doing it the other way around. Set the Load pin high initially, the Pulsout will then produce a pulse with the correct polarity.

[lerameur]

Tim,
How do you invert the CE signal with the PL pin. Do you direct connect both pins with an inverter? I guess my hardwireing is wrong...

K