Hi Nick,

The Timer 0 module is capable of counting signals up to about 50-MHz in asynchronous counter mode so you could probably get away with a single "divide by 2" prescaler in front of the T0CKI input if you want to use that counter for a 100-MHz input signal. An input gate "on" time of 20-msecs would provide 100 Hz counter resolution. An input gate "on" time of 200-msecs would provide 10-Hz resolution. You would need 24 bits to hold the 0..1,000,000 input counts (20-msec gate/100-Hz resolution) or to hold the 0..10,000,000 input counts (200-msec gate/10-Hz resolution). You would pull the least significant 8 bits from the 1:256 Timer 0 prescaler, the middle 8 bits from the TMR0 register, and the most significant 8 bits from a TMR0 "overflow" variable. With a 50-MHz input to Timer 0 (100-MHz divided by 2) and using a 1:256 Timer 0 prescaler, you can expect a TMR0 register overflow approximately once every 1.31 msecs so you would want to check for TMR0 register overflow at least that often during input gate "on" time.

Does that help? I've got assembler code for a Serial 12F683 50-MHz counter but I'm not sure that would be of any help to anyone here on the PBP forum.

Happy Holidays!

Cheerful regards, Mike