Originally Posted by
LinkMTech
I tried to change the FOSC to INTOSC with the various guesses:
Code:
@ __CONFIG _CONFIG1H, _FOSC_INTRC_1H
@ __CONFIG _CONFIG1H, _INTRC_OSC_NOCLKOUT
Also tried:
CONFIG1H=%00001000
You can find your .inc file here C:\Program Files\Microchip\MPASM Suite\P18LF13k22.INC
If it is not there, then download a newer mplab.
Here are the choices for the LF;
Code:
;----- CONFIG1H Options --------------------------------------------------
_FOSC_LP_1H EQU H'F0' ; LP oscillator
_FOSC_XT_1H EQU H'F1' ; XT oscillator
_FOSC_HS_1H EQU H'F2' ; HS oscillator
_FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high)
_FOSC_ECH_1H EQU H'F5' ; EC (high)
_FOSC_ERC_1H EQU H'F7' ; External RC oscillator
_FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator
_FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium)
_FOSC_ECM_1H EQU H'FB' ; EC (medium)
_FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low)
_FOSC_ECL_1H EQU H'FD' ; EC (low)
_PLLEN_OFF_1H EQU H'EF' ; PLL is under software control
_PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4
_PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control
_PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRTEN_ON_2L EQU H'FE' ; PWRT enabled
_PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal
_BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal
_BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal
_BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal
;----- CONFIG2H Options --------------------------------------------------
_WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register
_WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect.
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; RA3 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RA3 input pin disabled
_HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable.
_HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
_BBSIZ_OFF_4L EQU H'F7' ; 512W boot block size
_BBSIZ_ON_4L EQU H'FF' ; 1kW boot block size
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
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