It looks like part of the problem is Microchip not being consistent from chip to chip with their include file. Their P12f617.INC doesn't have these two lines:
The Message[303] warning looks like it is coming from the configuration bits word size, also in Microchip's P12F617.INC file. If you look at the bottom of the file, the config bits go up to FFFF. But if I look in the datasheet, it shows bits 0 to 13, or 3FFF.Code:;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' RP0 EQU H'0005' RP1 EQU H'0006' IRP EQU H'0007'
This could be bad advice (I have no way to test the chip), but it does compile correctly if I edit Microchip's P12F617.INC file so that all the config bits begin with a 3, instead of an F.
Code:;----- CONFIG Options -------------------------------------------------- _LP_OSC EQU H'3FF8' ; LP _XT_OSC EQU H'3FF9' ; XT _HS_OSC EQU H'3FFA' ; HS _EC_OSC EQU H'3FFB' ; EC _INTRC_OSC_NOCLKOUT EQU H'3FFC' ; Internal RC No Clock _INTRC_OSC_CLKOUT EQU H'3FFD' ; Internal RC Clockout _EXTRC_OSC_NOCLKOUT EQU H'3FFE' ; External RC No Clock _EXTRC_OSC_CLKOUT EQU H'3FFF' ; External RC Clockout _WDT_OFF EQU H'3FF7' ; Off _WDT_ON EQU H'3FFF' ; On _PWRTE_ON EQU H'3FEF' ; On _PWRTE_OFF EQU H'3FFF' ; Off _MCLRE_OFF EQU H'3FDF' ; Internal _MCLRE_ON EQU H'3FFF' ; External _CP_ON EQU H'3FBF' ; On _CP_OFF EQU H'3FFF' ; Off _IOSCFS_4MHZ EQU H'3F7F' ; 4 MHz _IOSCFS_8MHZ EQU H'3FFF' ; 8 MHz _BOR_OFF EQU H'3CFF' ; BOR disabled _BOR_NSLEEP EQU H'3EFF' ; BOR enabled in run, disabled in sleep _BOR_ON EQU H'3FFF' ; BOR Enabled
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