Oscillators, counts, clock cycles, config settings ......& women

[HankMcSpank]

Ok, I've now stripped both comparator interrupt handlers right back to the minimum - there's something very peculiar going on - which I don't just don't understand.

First here's a scope trace of what I'm feeding into the comparators...

green trace = comp1 input 1khz signal (the leading signal)
yellow trace = comp2 input 1khz signal (the lagging signal)



ok, when I enable just comp1 interrupts on their own,I get as near as damnit a count of 5,000 between comparator 1 interrupts (ie a perfect counting of clocks @1Khz).....

comp1=5002      comp2Time=0   
comp1=5000      comp2Time=0    
comp1=5001      comp2Time=0    
comp1=5002      comp2Time=0    
comp1=5002      comp2Time=0    
comp1=5001      comp2Time=0    

Here's the associated code snippets ...

@ INT_ENABLE  CMP1_INT     ; enable Comparator 1 interrupts
'@ INT_ENABLE  CMP2_INT

Comp1_Int:
        Comp1Time.Lowbyte = TMR1L +2   'Store away the timer1 count. 
        Comp1Time.Highbyte = TMR1H     'Store away the timer1 count.
        TMR1H = 0 'Set the high part of the timer value to 0
        TMR1L = 0 'Set the low part of the timer value to 0  
@ INT_RETURN


Comp2_Int:
        Comp2Time.Lowbyte = TMR1L 'puts the timer's low byte in MyTime's lower 8 bits 
        Comp2Time.Highbyte = TMR1H 'puts the timer's high byte in MyTime's upper 8 bits
        TMR1H = 0 'Set the high part of the timer value to 0
        TMR1L = 0 'Set the low part of the timer value to 0    
@ INT_RETURN

*BUT*

when I then enable comp2 interrupts (by uncommenting the enable comp2 interrupt line above - also commenting out the TMR1H = 0 & TMRLl = 0 in the comp1 interrupt, so that the timer now resets in the comp2 handler), it all goes wonky....

comp1=2959      comp2Time=4999 
comp1=2956      comp2Time=4999 
comp1=2956      comp2Time=4993 
comp1=2959      comp2Time=4999 
comp1=2954      comp2Time=4994 
comp1=2955      comp2Time=4995 
comp1=2958      comp2Time=4994 
comp1=2956      comp2Time=4996 

So comp1 count should be stored...the timer contunes on

I can't really account for what's going on here - there's almost nothing inthose interrupt handlers. equally there's plenty of time between the two signals for both handlers to easily finsih what they need to do before the next comparator interrupt arrives.

Perplexed