Quote Originally Posted by prstein View Post
Code:
'Make sure the Comparator 2 interrupt handler is disabled!
'Comparator1 Interrupt Handler++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
Comp1_Int:
        Comp1Time.Lowbyte = TMR1L  'Store away the timer1 count - this  will be the non lagged signal 'period' count.
        Comp1Time.Highbyte = TMR1H    
        TMR1H = 0                     'Set timer1 value to 0
        TMR1L = 0
        PIR2.6 = 0                     'Clear the Comparator C2 Interrupt Flag bit
Keep_Waiting:
        WHILE  PIR2.6 = 0         'Check to see if the Comparator 2 interrupt flag has flipped
            goto Keep_Wating
        WEND
        Comp2Time.Lowbyte = TMR1L    'Store away the timer1 count again (ie once the lagged signal leading edge arrives - this is the lag count)
        Comp2Time.Highbyte = TMR1H    
@ INT_RETURN
You could also add some sort of check so that it would exit the loop if an unreasonable amount of time has elapsed.

Best Regards,
Paul
I like Pauls approach, Seems to be the least amount of time between Comp1 and 2. one thing I would do, is program his while loop in ASM. This is because I have no idea how many instructions it takes using PBP. I think this will mask the issue of how long it takes to actually enter the handler. Which is what I think above folks are reffering to with the PBP include.

heres the while loop in asm:
Code:
     BCF PIR2,6       --> clears the comp 2 int flag
HERE                    --> label to jump to
     BTFSS PIR2,6  --> test if comp 2 int flag is set
     GOTO HERE     --> not set, go back to test
CONTINUE            --> Comp 2 int occured, do what ever needs to be done
The above will take exactly 1 instruction to enter the loop, then 3 inscrutions to to run per loop. now for some math:

you are running a 20mHz clock, so thats 5MIPS. so 1 instruction takes .0000002 sec to execute. At 1400 htz, each cycle takes .0071428 sec. that devided by 360 = .00000198sec per degree. so you should be able to measure to almost .5 degree. assuming comp2 fires between BCF and BTFSS, thats 3 instrution cycles, or .0000006 sec.(I think BTFSS may take 2 cycles when true)

Someone please check my math, but these numbers show you have far too much overhead somewhere that can only be explained by the above posts.