I use a 16f690 @20Mhz
The 16F690's Comparator 1 receives the non lagged signal (set to internal VREF to trip at about 1/2 VCC)
The 16F690's Comparator 2 receives the phase lagged signal (set to internal VREF to trip about 1/2 VCC too)
Identical signals are fed into both comparators (bar the phase lag)
DT's interrupts enabled for CMP1 & CMP2.
On the scope the lag time measures about 20us - below which Comp2 will not decrement.
I don't know enough about what's going on under the hood wrt interrupts (or timer1 zero-ing) to shine any more light on why the comp2 count won't go below 336...when clearly it should as the leading edge of the lagged signal gets close to zero lag. So being a bit wet nehind the ears, is there any other possible method I can use that circumvent this problem?
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