Serin after instant interupt?

[richard]

the likely hood of getting serin/debugin/ser2in to sync up within 4 or 5 bytes
when isr triggered by start bit is very low


my strategy would be to
create a buffered single byte serial input routine edge triggered by interrupt.
the routine could then react with the assumption that start bit is underway.






to flesh it out further one would need to know :-
baud rate
inter byte delay if any
size of and timing of data "parcels"
start and/or end markers if any
any crc or other indication of successful reception

[retepsnikrep]

Thanks for the input.

Incoming data is standard 9600,8,N,1
Interbyte delay 80us
Packets are 5 bytes long.

1) Header (I know what this will be so could skip/lose this byte)
2) Length (5)
3) Data 1
4) Data 2
5) Checksum (I know the header byte even if it is corrupted/lost so can still calculate the checksum)

[richard]

if your data looks like this


and your chip is fast enough

a isr routine like this [clear the flag, set inx to zero, set edge index active and off you go]
when flag set you have a pkt



might work in pbp



i would do in asm though