Quote Originally Posted by Macgman2000 View Post
; Save and restore FSR and any other registers used
bcf T1CON.0 ; stop timer 1
bcf PIR1.0 ; clear over flow flag
...
bsf T1CON.0 ; re-enable timer 1
bcf PIE1.0 ; clear overflow flag just in case
endasm
At the ASM level, bits are separated from the register with a comma instead of a dot like with PBP.

bcf T1CON,0
bcf PIR1,0
bsf T1CON,0
bcf PIE1,0

However ...
Your ISR does not restore context.
The enable bit is cleared, when the comments say "; clear overflow flag just in case".
An unknown value is moved to address 0 (movwf 00h). Address 0 is usually a PBP system variable.
And the values in TMR1L:H are moved into WREG and nothing is done with them (movf TMR1x,W).

So, beyond the reported errors ... it's not going to work.
Try DT_INTS-14 v1.00.