Make sure you're in the correct register banks, and it should work just fine. Show whatever code you're having issues with, and someone can probably offer help.
PIE1 is not in the same register bank as the rest of the registers you're writing to.
Make sure you're in the correct register banks, and it should work just fine. Show whatever code you're having issues with, and someone can probably offer help.
PIE1 is not in the same register bank as the rest of the registers you're writing to.
Last edited by Bruce; - 23rd July 2010 at 01:32.
Hello Bruce,
I am not doing anything that didn't work for the 16F877A. The compiler returns errors for this
code segment. These are the items it returns errors for...T1CON.0 , PIE1.0 and PIR1.0
See below.
[ code]
ASM
myint
; Save and restore FSR and any other registers used
bcf T1CON.0 ; stop timer 1
bcf PIR1.0 ; clear over flow flag
movwf 00h ; load timer for 16,535 * 8 prescaler interrupt on 16 bit timer
movf TMR1H,W
movf TMR1L,W
bsf T1CON.0 ; re-enable timer 1
bcf PIE1.0 ; clear overflow flag just in case
retfie ; Return from interrupt
endasm
[ /code]
Unfortunately, that doesn't really mean much since this PIC type is a totally different animal...I am not doing anything that didn't work for the 16F877A
Post everything you have, and I'll give it a shot here compiling it. And - like I mentioned above, not all registers are in the same banks on this PIC as they are in the 877A, and just trying to cut & paste something that was working on an 877A for sure isn't going to work.
This new series PIC is BIG time different than the 877A.
At the ASM level, bits are separated from the register with a comma instead of a dot like with PBP.
bcf T1CON,0
bcf PIR1,0
bsf T1CON,0
bcf PIE1,0
However ...
Your ISR does not restore context.
The enable bit is cleared, when the comments say "; clear overflow flag just in case".
An unknown value is moved to address 0 (movwf 00h). Address 0 is usually a PBP system variable.
And the values in TMR1L:H are moved into WREG and nothing is done with them (movf TMR1x,W).
So, beyond the reported errors ... it's not going to work.
Try DT_INTS-14 v1.00.![]()
DT
Interrupts on these are easier than older 16F parts with the auto restore feature, but you need to make sure you're flipping the right bits to set everything up properly....
Try this.
Then check out DT_INTS-14 v1.00Code:ASM __config _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_ON & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF __config _CONFIG2, _PLLEN_OFF & _LVP_OFF & _STVREN_OFF ENDASM DEFINE OSC 8 DEFINE INTHAND Tmr1Int OSCCON= %01110000 GOTO Init ' jump over interrupt routine ASM Tmr1Int ; retfie auto-restores w, status, bsr, fsr and pclath bcf T1CON,TMR1ON ; stop timer 1 bcf PIR1,TMR1IF ; clear over flow flag movlw 0xBF ; load timer for 16,535 * 8 prescaler interrupt on 16 bit timer movwf TMR1H ; load high byte movlw 0x69 movwf TMR1L ; load low byte bsf T1CON,TMR1ON ; re-enable timer 1 movlw 0x01 xorwf PORTB,f ; toggle RB0 retfie ; Return from interrupt ENDASM Init: PORTB = 0 TRISB = 0 CM1CON0.7=0 CM2CON0.7=0 ANSELA = 0 ' all digital. A/D disabled ANSELB = 0 PIR1 = 0 ' clear TMR1 int flag PIE1 = %00000001 ' TMR1 int enabled INTCON = %11000000 ' global & peripheral ints enabled T1CON = %00110001 ' TMR1 1:8 prescale, timer1 on Main: HIGH 1 PAUSE 1000 LOW 1 PAUSE 1000 GOTO Main END
Last edited by Bruce; - 23rd July 2010 at 12:56.
Hello Bruce, Darrel,
Thanks for your help! I read in the data sheet that the context saving is done automatically. So unlike
the 16F877A where a context saving routine example is featured, the 16F1827 does not have any
such routine listed in the data sheet. Just a few lines that mention automatic context saving.
So, using PBP do I need to use context saving using the ASM ISR ?
Nick
Nope. If you're using the 16F1827 you don't need to save w, status, bsr, fsr or pclath. It does this for you automagically...So, using PBP do I need to use context saving using the ASM ISR ?![]()
OOPs, there's no FAST option on RETFIE with those chips.
It always restores them.
My Bad!![]()
DT
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