Kamikaze47's numbers are theoretically correct, and it will appear to work.
However, this is the reason I never added OSC frequencies above 20mhz to the Elapsed timer ...
Anything over 24mhz would require a prescaler to get 100hz interrupts.
And every time you reload the Timer, the Prescaler gets cleared.
With a 1:8 prescaler, it could lose up to 7 counts on every interrupt.
At 100 hz, it could lose up to 700 counts every second. That's 70uS with 40mhz OSC.
Not good for a clock, especially in the long term.
I was thinking about it yesterday and realized that I could make a software "postscaler" in the ISR and run the interrupts at higher frequencies for the chips running >24mhz.
So that's what I did.
The attached version of Elapsed_INT-18.bas (ver 1.2) should work with any OSC.
The TimerConst is now calculated automatically instead of using "constants".
The Timer is always 1:1, and at 40mhz will run at 200hz.
Then the handler counts off 2 groups of 100 ticks (1:2 postscaler).
@ 64mhz the timer is 400hz, with a postscaler of 1:4.
You can use the INT_Handler as an ASM "type" interrupt to save overhead.
I've only had it running a few hours @40mhz, but it seems to be keeping time really well. (better than my PC).
We'll see what it's like after a few days.
hth,
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