Clear Command stops 18F4525 dead

[Bruce]

CLEAR should still work! What are your config settings when using the 18F4525?

[khufumen]

Configuration commands I am using are:

Oscillator = INTRC (INTIO2)
Fail Safe Clock Monitor = Disabled
Internal External Switchover = Disabled
The configuration settings I am using are:

Powerup Timer = Disabled
Browout Reset = Enabled, SBOREN Disabled
Brownout Reset Voltage = 4.2V
Watchdog Timer = Enabled
Watchdog Timer Postscaler = 1:2
CPP2 Multiplexed with B3
PORT B Reset State = Digital I/O
Low Power Timer1 Oscillator = Higher Power
MCLR Pin Function = Input Pin
Stack Overflow / Underflow Reset = Enabled
Low Voltage Programming = Disabled
Enhanced CPU = Disabled

[Bruce]

See if CLEAR works with the watchdog timer disabled. With a WDT postscaler of 1:2 and a WDT timeout period of 4mS x the postscaler, you only have ~8mS before the WDT times-out and causes a reset.

The CLEAR macro doesn't have clrwdt instructions, and it takes ~9.91mS to clear all RAM in this part, so it resets before it has time to clear RAM. You can also bump-up the postscaler to something > 10mS, and it should work.