Sounds like a really challenging and interesting project. I have been working with LPC176x Cortex M3 devices. Some pertinent specs, not bad for a $6 chip:
a. ARM Cortex-M3 32-bit processor, running at 100 MHz - single cycle.
b. Nested Vectored Interrupt Controller (NVIC).
c. 512 kB on-chip flash programming memory, 64kB total RAM.
d. Eight channel General Purpose DMA controller that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
e. Ethernet MAC with RMII interface and dedicated DMA controller.
f. USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller.
g. Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.
h. CAN 2.0B controller with two channels..
j. SPI controller with synchronous, serial, full duplex communication and programmable data length.
k. Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s.
l. 70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors.
m. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins.
n. Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs.
p. One motor control PWM with support for three-phase motor control.
q. Quadrature encoder interface that can monitor one external quadrature encoder.
r. One standard PWM/timer block with external count input.
s. RTC with a separate power domain and dedicated RTC oscillator - includes 20 bytes of battery-powered backup registers.
t. Repetitive interrupt timer provides programmable and repeating timed interrupts.
u. Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
v. Code Read Protection (CRP) with different security levels.
w. Unique device serial number for identification purposes.
x. Standard JTAG test/debug interface for compatibility with existing tools.
y. Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
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