# ARM Cortex-M0 processor, running at frequencies of
up to 50 MHz and 48DMips
# ARM Cortex-M0 built-in
Nested Vectored Interrupt Controller (NVIC)
# 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) on-chip flash programming memory
# 8 kB, 4 kB, or 2 kB SRAM
# In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software
# UART with fractional baud rate generation, internal FIFO, and RS-485 support
# Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only)
# I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode
# Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors
#
Four general purpose 16/32-bit timers/counters with a total of four capture inputs and
13 match/PWM outputs
# Programmable WatchDog Timer (WDT)
#
System tick timer
# Serial Wire Debug
# High-current output driver (20 mA) on one pin
# High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus
# Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes
# Three reduced power modes: Sleep, Deep-sleep, and Deep power-down
# Single 3.3 V power supply (1.8 V to 3.6 V)
# 10-bit ADC (400ks/S) with input multiplexing among 8 pins
# GPIO pins can be used as
edge and level sensitive interrupt sources
# Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock
# Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins
# Brownout detect with four separate thresholds for interrupt and one threshold for forced reset
# Power-On Reset (POR)
# Crystal oscillator with an operating range of 1 MHz to 25 MHz
#
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock
# PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the watchdog oscillator.
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