Break up your delays into shorter PAUSE times so it can react to each interrupt faster, and
don't mess with INTCON.7 when using ON INTERRUPT.
PBP places a RETURN at location 4 (hardware interrupt vector), so INTCON.7 gets left clear
and this lets PBP know an interrupt needs to be serviced.
INTCON.7 is automatically set on return from your interrupt handler. If you set INTCON.7 in
your code, after ON INTERRUPT is used, PBP assumes the interrupt has already been
serviced.
See if this helps;
Code:
DEFINE NO_CLRWDT 1
DEFINE OSC 4
Include "modedefs.bas"
led VAR gpio.1
i VAR BYTE
X VAR WORD
@ __CONFIG _INTRC_OSC_NOCLKOUT & _WDT_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_ON & _BOD_ON & _CPD_ON & _IESO_OFF & _FCMEN_ON & _WUREN_OFF
main:
' Initialize the processor
TRISIO = %111000
GPIO = 0
CMCON0 = 7
INTCON=128
OPTION_REG =%10000111 ' RAPU = off, PS 1:256 to TMR0 (overflows in 256*256*1uS) 65.536 mS
pcon.5=0
pie1=0
t1con.0=0
i=0
ON INTERRUPT GOTO start
pause 50
check:
if gpio.5=1 then ' Takes GP0 high BUT not low
toggle gpio.0
'pause 300 ' TMR0 will overflow long before this PAUSE is finished
FOR X = 1 TO 300 ' 300mS PAUSE in 1mS increments
PAUSE 1
NEXT X
while gpio.5
pause 1
wend
endif
if gpio.4=1 then ' Independently working fine BUT also takes low gp.0 if it's high only
toggle gpio.1
'pause 300 ' TMR0 will overflow long before this PAUSE is finished
FOR X = 1 TO 300 ' 300mS PAUSE in 1mS increments
PAUSE 1
NEXT X
while gpio.4
pause 1
wend
endif
if gpio.3=1 then
gpio.2=1
'pause 100 ' TMR0 will overflow long before this PAUSE is finished
FOR X = 1 TO 100 ' 100mS PAUSE in 1mS increments
PAUSE 1
NEXT X
while gpio.3
pause 1
wend
TMR0=0
INTCON.5 = 1 ' enable TMR0 overflow interrupt
endif
goto check
disable
start:
i=i+1
INTCON.2=0 ' clear TMR0 overflow interrupt flag bit
if i=77 then
gpio.2=0
i=0
' INTCON=128 ' INTCON.7 gets set on return from here
endif
resume
Bookmarks