If you are using PBP 2.50 or later there is a define that handles that for you ...
Code:
DEFINE WRITE_INT 1
For PBP versions prior to 2.50 you can disable global interrupts, but this will cause a delay of up to 4 mS during the self-timed write process.
Code:
INTCON.7 = 0
WRITE  ADD, VAL
INTCON.7 = 1
Sometimes it's better to just try the WRITE, then READ it back and see if it wrote the correct value, if not ... try again.

To interfere with the write sequence, an interrupt must occur within a 4-instruction window (4 uS with 4Mhz OSC) while it's setting up the write to EEPROM. That doesn't happen very often, and waiting 4000 uS (4 mS) just to make sure nothing happens in that 4uS can cause you to miss interrupts.