Hi! I've been cathing up on theory, and have questions regarding the inner/electrical workings of the ADC module and Chold (Sample and Hold Capacitor).

reading through various documents (for example ww1.microchip.com/downloads/en/AppNotes/01298A.pdf)
I'm left with some uncertainties.

It is currently my understanding that simply pointing to the correct ADC Channel (via ANSEL Analog Select bits) will connect and charge/discharge CHOLD to the level at that pin. In the beforementioned reference that pin is
a driven digital output so Chold is charged to Vdd....

I'm guessing the Analog Select Bits directly control the Sampling Switch Rss. So its also possible to sample....and then disconnect CHOLD via ANSEL and still start a conversion via the godone bit?
I also assume disconnecting CHOLD only works as long as the go/done bit hasen't been set yet..

"Sampling and Conversion: After a new channel
is selected, a minimum amount of sampling time
must be allowed before the GO/DONE bit in
ADCON0 is set to begin conversion. Once
conversion begins, it is OK to select the next
channel, but sampling does not begin until current conversion is complete!
....."

I'd be greatful for any pointers...
(unfortuntely I don't have my electronics nearby to gain insight... would have been a quick test of a Vref...)

greets mike