Hey guys, will this work?

[jmgelba]

YES!! I understand at last!! Thank you so much for your time Steve.

I have been looking at it all wrong. I can see moving the bits now. I thought each bit value, a 0 or a 1, was the 4 and 5 bit part of the number, so when you removed the lsb's, you shifted everything, and what was in 6 and 7 is now in 4 and 5 and is the new state.

[jmgelba]

Well now, of course, this does absolutly nothing!
Here's the complete code.

OSCCON = $70
define osc 8

CSET   VAR WORD 'CURRENT SET
CSEN   VAR WORD 'CURRENT SENCE  
DUTY   VAR wORD 'PWM DUTY CYCLE

ADCON0 = %00011001
ADCON1 = %00001111
ADCON2 = %10111111
TRISA = %00000000
TRISB = %00110011
Define  ADC_BITS        10     	' Set number of bits in result
Define  ADC_CLOCK       3     	' Set clock source (5=fosc/16)
Define  ADC_SAMPLEUS    10    	' Set sampling time in uS

CSET = 0
CSEN = 0

duty = 20                           ' duty value for 50% duty cycle
PR2 = 9                             '
T2CON = %00000100                   ' timer2 on, prescale 1:1
CCPR1L = duty>>2                    ' MSB of duty cycle value
CCP1CON.4=Duty.0                    ' set PWM mode and store the 
CCP1CON.5=Duty.1                    ' 2 LSB of duty

LOOP:
ADCIN 6, CSET 'READ VALUE OF CURRENT SET POT
ADCIN 4, CSEN   'READ VALUE OF CURRENT SENCE
IF CSEN > CSET Then LET DUTY = DUTY - 1
IF CSEN < CSET THEN LET DUTY = DUTY + 1
CCPR1L = duty>>2                    ' MSB of duty cycle value
CCP1CON.4=Duty.0                    ' set PWM mode and store the 
CCP1CON.5=Duty.1                    ' 2 LSB of duty
GOTO LOOP