Am I crazy thinking that this shouldn't have been something I had to fight with? There is a possibility that the pic will have voltage on the analog pin before Vdd when the entire circuit is powered up,
Nope, you're not crazy. This is very typical of MCUs, FPGAs, and in particular ADCs. The inputs are diode protected (from datasheet "I/O pins have diode protection to VDD and VSS"), so if you apply power to the I/Os before applying power to the "core" guess what. You run the chance of reverse biasing the protection diode, and thus biasing the device through the I/Os.

The best approach would be to not apply power to the I/Os before applying power to the "core" (i.e. make sure there is no possibility "that the PIC will have voltage on the analog pin before Vdd when the entire circuit is powered up"). This is sometimes inevitable, in which case you have to work around it. Buffering the I/Os is always the second best option. As an example, for the digital I/Os of an MCU you can use logic buffers (gates, latches, etc) which get turned on by the MCU after it has been powered-on; this way the I/Os are effectively buffered from the external world (sometimes series resistors could do the trick - but you never know). For analog I/Os you could use OPAMPs (again, which get turned on by the MCU). These are just suggestions, and I'm sure there will be others. But the main thing is that you are not going crazy, and this is something which has been tackled before time and time again.