Quote Originally Posted by Darrel Taylor View Post
OK, then let me throw some fuel on the fire...

<img src="http://www.picbasic.co.uk/forum/attachment.php?attachmentid=3293&stc=1&d=123853748 1" /><!-- Attachment 3293 -->

This is the "Full control" version.
I've connected the pulse input to the INT pin of the PIC, for the delayed pulses.

The second input of the first NAND goes to another PIC pin (Zero Delay Enable).
When that pin is HIGH, Zero Delay is selected and the output of the flip-flop will go high immediately on an incoming pulse.
R1 keeps it disabled till the PIC takes over.

Another pin is used to "Set from CPU".
This is used to Set the output Flip-Flop manually from the PIC so it can respond to Delayed pulses timed by the interrupts. Taking the pin LOW will set the flip-flop. This should be tri-stated when in Zero Delay mode.

Clearing the flip-flop (end of pulse width) is done with the CCP out pin. Whether it's actually the CCP doing it, or timed interrupts.

Again, Purely theoretical.
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Hmm, how would one use this for falling edge trigger? I'll be honest, I havent had time to study what you are doing here, but what I've looked at seems logical.
I just ordered a couple of quad nands and a few 40MHz resonators, and over the next week or so will have a chance to work with this.