555? Eeewwwww!
I think the minimum monostable time is around 2uS.

Actually, for the 0 delay, I was thinking you could do it with some 74HC NAND gates. A little tricky though.

By creating a SET/RESET flip-flop that gets toggled immediately on the incoming pulse, it can "gate" the FOSC/4 out signal into Timer1.

With a CCP module in COMPARE mode, you can load the delay time in CCPRxL:H prior to the pulses, and when it sees a match, it will output a pulse on the CCP pin which will reset the flip-flop, turning off the final pulse with great precision, and no software delay.

Interrupts will probably still be needed to reset things for the next pulse, but the actual task is done by hardware.
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