How instant are Instant Interupts?

[jmgelba]

New project, in the "Is this even possible?" stage.
Hardware is open to sugestion.

I need to send out a pulse of any of the following durations depending upon settings: 1, 3, 5, 10, 30, 50, 100, 1000, 3000, 5000, 10000uS.

I need a delay before the pulse is sent out of any of the following: 0, 20, 50, 100uS.

Trigger input is TTL 5V rising or falling edge, selectable.

I want to have a 2x8 LCD display and a few buttons to set up a menu to change and set all these options. On completion of saving the settings, a button can be preesed to activate and wait for an incoming pulse. That would be the main program.

I need high accuracy on the o/p pulse delay and duration as this is a strobe light application for high speed cameras running 10,000 plus frame rates per second.

Are Instant Interupts up to the task?

[Darrel Taylor]

Everything but the 0 delay before the pulse.
It would take external hardware for that.

Assuming an 18F with high priority ASM type interrupts at high OSC speed.
The rest should be possible.

So the next question will be ...
What is the exact interrupt latency?

And the best way to answer that is to have you set up a timer with 1:1 prescaler triggering an interrupt.
When the timer rolls over to 0, an interrupt is generated and the timer continues counting.

When it reaches the handler, immediately turn the timer off.
The value in the timer now has the exact number of instructions it took to get there (+1).
It should be around 30-40 instructions. @ 40Mhz, that's 3-4 uS.
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[jmgelba]

Yeah, the 0 delay is going to be fun.

I'd thought about something along the lines of a 555 setup as a one shot with a couple of caps that can be switched in to the circuit to get the low uS delay and pulse width. Caps are switched in or out with FET's thus having control through the menu system.

Everything else is ran through the PIC timers.

[Darrel Taylor]

555? Eeewwwww!
I think the minimum monostable time is around 2uS.

Actually, for the 0 delay, I was thinking you could do it with some 74HC NAND gates. A little tricky though.

By creating a SET/RESET flip-flop that gets toggled immediately on the incoming pulse, it can "gate" the FOSC/4 out signal into Timer1.

With a CCP module in COMPARE mode, you can load the delay time in CCPRxL:H prior to the pulses, and when it sees a match, it will output a pulse on the CCP pin which will reset the flip-flop, turning off the final pulse with great precision, and no software delay.

Interrupts will probably still be needed to reset things for the next pulse, but the actual task is done by hardware.
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[jmgelba]

No I'd never use a 555 timer but I though about something along the same lines. In the past, the way way past, I had a project that used some really high stability and acurate timing IC's. I think the part number began with Z.
Anyway, I do agree that hardware is the way to go for the 0 and 1uS delay.

I've never used a PIC timer or a ccp so this should be good for learning.

[Darrel Taylor]

... I've never used a PIC timer or a ccp ...

Then you won't want to do this.
But here's what I was thinking in post#4 ...

<img src="http://www.picbasic.co.uk/forum/attachment.php?attachmentid=3287&stc=1&d=123847625 4" /><!-- -->

This would be for Zero delay only, just to show the concept.
But it only takes a couple changes to get full control (zero delay or interrupt timed, selectable).

Some PIC's have a Gated Timer1 built into the chip. That would make the OSC config easier, and it wouldn't need the lower NAND gate.

Zero Delay or Full Control, it still only takes one 74HC00, and the mode is selected by the PIC.

Purely theoretical.
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