Is it possible to capture the TMR1 counts without a CCP and still let the counter continue?
The problem: Trying to use a 18 pin chip for space, currently a 18F1330.
I need the Power Control PWM as I need at least 2 different PWMs, three would be better.
The TMR1 is using a prescaler of 1:1 and a preload of 5543 (@8mHz) for a cycle of about 30 mS.
That cycle sends a ultrasonic transmit pulse and starts looking for a return echo.
INT2_INT (eventually CMP2_INT) is used to catch the echo and grab the count from TMR1. I spent the last 6 hours learning that when you load TMR1, you need to load TMR1H first, before TMR1L. I won't tell you how many times I read the datasheet before I realized that one. I have the cycle stable now, but the capture of the elapsed time is still wonked. I can't see where.
I could go to a 18F2331 and get CCP and PCPWM, but that puts me at 28 pin and I really don't have the room.
If anyone sees something that here, I sure would appreciate the advice.
Code:
'******************************************************************
'* Name : CS-Sonic1330_2f.BAS *
'* Author : Mark A.Rokus *
'* Notice : Copyright (c) 2009 Controlled Surroundings Inc. *
'* : All Rights Reserved *
'* Date : 3/25/2009 *
'* Version : 1.0 *
'* Notes : 18F1330 @ 8mHz, PBP 2.50b, MCS 3.0.0.0
'* Pulse out on PORTB.0 every ~30 mS (TMR1: _Transmit)
'* external circuit echos back pulse on PORTB.2 (INT2)
'* between 3mS and 23mS. After transmit, enable INT2_INT and
'* get count to "EchoTime". Send # out on HSER to debug.
'* This is the core of the code that is failing. Increasing the
'* result count with every echo while the return pulse is steady????
'****************************************************************
DEFINE OSC 8
DEFINE HSER_RCSTA 90h
DEFINE HSER_TXSTA 24h
DEFINE HSER_BAUD 9600
DEFINE HSER_CLOERR 1 ' automatic clear overrun error
clear
TRISB = %01000100 ' PWM1,3,5 outputs,RB2=INT, RB0,2,3: DIO
ADCON1 = %00001111 ' Set up ADCON1 no matter what you're doing!!!!!!
T0CON = %10001000 ' On, 16 bit, Prescaler Bypassed (1:1)
T1CON = %10000001 ' 16bit, 1:1 ps, 30 mS INT
CMCON = %00000100 ' CMEN2 to enable the comparator
CVRCON = %10100010 ' REF on, REF voltage @ 1.563
RCON = %00011111 ' NO Priority for interrupts
OSCCON = %11111110 ' INTOSC, 8MHz,
hserout [" 1330-2g",13,10]
'::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
INCLUDE "DT_INTS-18.bas" ' Base Interrupt System
INCLUDE "ReEnterPBP-18.bas" ' Include if using PBP interrupts
'::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
' Variable definition
'::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
EchoTime Var word
PL1lo con $A7 ' Preload for TMR1 LO byte, Cycle time
PL1hi con $15 ' Preload TMR1 HI byte ,PL =5543/ 1:1
ASM
INT_LIST macro ; IntSource, Label, Type, ResetFlag?
INT_Handler INT2_INT, _GetEcho, PBP, yes ;straight I/P
INT_Handler TMR1_INT, _Transmit, PBP, yes
endm
INT_CREATE ; Creates the interrupt processor
ENDASM
'@ INT_ENABLE INT2_INT
@ INT_ENABLE TMR1_INT ; enable Timer 1 interrupts
'***************************************************************************
Start:
Mainloop:
hserout [#EchoTime,13,10]
pause 500
goto Mainloop
'*********** Int handlers **************************************************
'---[INT - interrupt handler]-----------------------------------------------
' TMR1 cnt up from start of TX. INT when RX, get counts into EchoTime
GetEcho:
T1CON.0=0 ' Stop TMR1
echoTime.Highbyte=TMR1H ' capture the counts
echoTime.Lowbyte=TMR1L
' echoTime.Highbyte=TMR1H ' capture the counts
T1CON.0=1 ' Restart the TMR1 to finish cycle
@ INT_RETURN
'---[TMR1 - interrupt handler]-------------------------------
' TMR1 = 16 bit, 1:1, 65535 - 5543(preload) ~30 mS cycle
Transmit:
@ INT_DISABLE INT2_INT ; Disable external ints to stop Echo RX
'T1CON = %10000001 ' 16bit, 1:1 ps, 30 mS INT
TMR1H = PL1hi 'Preload HI byte
TMR1L = PL1lo 'Preload LO byte =
asm
BSF PORTB,0
NOP ; need 7 NOPs between changes for 125kHz @ 8mHZ
NOP
NOP
NOP
NOP
NOP
NOP
BCF PORTB,0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
endasm
@ INT_ENABLE INT2_INT
@ INT_RETURN
end
Thanks
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