PICs and harsh environments


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  1. #1
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    use this diagram, I forgot to add a few things..
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  2. #2
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    R3 and R4 will give you some problem, this makes a great voltage divider but will give you false logic level.

    Is this a Typo or those 220nf are 220uF?
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

  3. #3
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    something is weird in the way you hook Q3 and Q4
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

  4. #4
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    Yeah, GND must be Vdd...

    Ioannis

  5. #5
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    yea, no idea what i was thinking when i threw those together, I had it differently just read my notes wrong, really wrong... anyhow, look at this one
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  6. #6
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    lol, forgot to hook up Q4.... anyways it should be connected to an LED.

  7. #7
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    really not liking the CAD software I am using, its tough to read.

  8. #8
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    Definitely better, but... Q1 and Q2 are not connected the proper way, the emitter should go to GND, I'll assume a lack of sleeping for this one

    I would suggest few things
    1. add a 0.1uF capacitor at the regulator input
    2. assuming Q3 drive a relay (because i'm not sure of the symbol you're using), I would suggest, if at all possible to use a 12V relay, this will keep spikes far of the logic Vdd. OR, depending how much current your relay coil need, and if have tons of those, add a resistor in serie with the 12v line...
    3. D1 is a good idea as long as your load on J4 don't overload the maximum forward current, which is ~1A.
    4. Depending how much current and where your LED take it's voltage, you may don't even need Q4
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

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