LOW RESET
PAUSE 5
HIGH RESET
PAUSE 300
LOW RESET

The second LOW RESET keeps the device in RESET during the transfer, it should not be there.

The CLK rate of SHIFTOUT is 50khz or higher, but the device is expecting no more than 500 hz clk (2ms per bit).
To slow it down, add ...
Code:
DEFINE SHIFT_PAUSEUS 2000
PortA.4
|
10K
|
10K
|------ CLK - SD20 - P04
10K
|
Gnd
Your voltage divider is only supplying 1.6V to the inputs (when High), and All inputs to the WTV020-SD-16P have internal Pull-up resistors of unknown value. So when the PIC's output is low the 10K resistor will be fighting the pull-up and probably doesn't go low enough.

A better way would probably be to not use SHIFTOUT and send each bit and clk in a FOR loop. Then you can use LOW and INPUT and remove the voltage dividers completely. Just remember, NEVER use HIGH or SHIFTOUT or TRIS when directly connected.