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KBLIM, in the attached schematic there are two suggestions for your project:
First suggestion: Modify the relay driver, in your shematic the base current is the collector current. The base of the PNP transistor should be polarized (pulledup) and the base current limited with a resistor. I don't think these two transistors will last long wired as per your schematic.
Second suggestion: How to solve, in a simple way, your current reading problem.
Al.
All progress began with an idea
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Thank you, aratti.
Really appreciate your suggestion 1 and 2. Your suggestion one really help me to protect my resistor and the opto couple.
However please forgive me because didn't give the connection on low ohmic resistor to measure Vi. Because of the site condition, the resistor must be connected between the positive source and the load.
13.8V 0-------------^^^Vi^^^------------====Load=====-------------0 0V
Therefore the suggestion 2 is not suitable for my case. The 0V will not be suitable to be my Vref- in the ADC configuration. Just wonder how :
1. How do i setup the ADC to measure the Vi. The source is 13.8V, but pic is powered by 5V in my design.
2. The PIC is configured in VREF+ = AVDD, VREF- = AVSS to measure others voltage reading, what do i need to change for the VREF in order to measure Vi.
Again very thank you to aratti!
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If you cannot mount the resistor on low side, read this application note perhaps you will find the solution.
Al.
http://www.zetex.com/3.0/appnotes/apps/an39.pdf
Last edited by aratti; - 1st December 2008 at 19:13.
All progress began with an idea
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Thank you aratti, I will study the pdf.
By the way, what is the maximum Vref-, Vref+ and the voltage the pic can measure?
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