Dual clock speeds on a PIC

I need to have the lowest power possible while logging data for up to a year on a small 3.6 volt lithium battery but I also want a fast download to dump the very large data file of 128 MBytes after the data logger has been retrieved many months after deployment. Can I have a PIC running on a 100 KHz crystal while in data gathering mode and just force an external 20 MHz clock into CLKI/OSC1 for the data dump phase. I want to leave the 100 KHz crystal in place between OSC1 and OSC2 and just force a 1 volt peak to peak 20 MHz signal in for the data unload phase.

Has anyone tried this dual clock speed approach before? Any problems I should look out for?

BrianT

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Originally Posted by BrianT

Can I have a PIC running on a 100 KHz crystal while in data gathering mode and just force an external 20 MHz clock into CLKI/OSC1 for the data dump phase. I want to leave the 100 KHz crystal in place between OSC1 and OSC2 and just force a 1 volt peak to peak 20 MHz signal in for the data unload phase.

Has anyone tried this dual clock speed approach before? Any problems I should look out for?

BrianT

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I don't think you can use the dual crystal idea because a low speed crystal uses XT config setting (low drive current), whereas a 20Mhz crystal would use HS. High drive current which low speed crystals don't like, might work, but might drift a bit. Conversely, you might get lucky and be able to get a 20Mhz crystal to run off the XT setting.

Now, if you used 2 separate external DIP oscillators...that's a different story...
A couple of 2 input AND gates...a 7408 or a couple of those SOT-23 package single gate logic chips, I think Fairchild calls them 'Tiny Logic'.
One AND gate uses input A as an enable along with input B from 100khz clock
2nd AND gate uses input A as the enable for the other clock (as well as power for the oscillator maybe?) along with input B from the 20Mhz clock.
If you're using a PIC with a built-in clock fail oscillator (usually runs at 37-40khz), you could switch to that while switching main clock speeds, which would basically solve the problem of start up.
Or maybe skip the AND gates all together and just power on a 20Mhz DIP oscillator and force it over the top of the 100khz clock. Might look a bit ugly on a 'scope though.

I do that on my '4620. External 10Mhz, using 4xPLL, internal @ 40Mhz. When I don't need the processing power, I go to the internal 8Mhz. When I really don't need the power, I go to the internal ~37Khz.

Don't know what kind of PIC you're going to use, so we don't know what kind of options are available...

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Originally Posted by BrianT

I need to have the lowest power possible while logging data for up to a year on a small 3.6 volt lithium battery but I also want a fast download to dump the very large data file of 128 MBytes after the data logger has been retrieved many months after deployment. Can I have a PIC running on a 100 KHz crystal while in data gathering mode and just force an external 20 MHz clock into CLKI/OSC1 for the data dump phase. I want to leave the 100 KHz crystal in place between OSC1 and OSC2 and just force a 1 volt peak to peak 20 MHz signal in for the data unload phase.

Has anyone tried this dual clock speed approach before? Any problems I should look out for?

BrianT

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The easy answer is to use a PIC with an internal oscillator. You can run most of them at eight different speeds from 31.25khz or 125khz & doubling on up to 8MHz. Run it as slow as you want for gathering mode, and 8mhz for downloading--you can change the clock speed on the fly by changing the OSCCON register.

For even more power saving, put the PIC to sleep, and wake up periodically. A PIC and a 32khz watch crystal works well as an RTC, and is even documented on the microchip site.

Thanks Tenaja and Skimask. Some more details might clarify.

The processor is an 18LF4620 TQFP. It spends most of its time asleep where it draws 2.6 uA with a 4 MHz xtal. It runs at about 4 mA plus the external signal conditioners on a 4 MHz xtal. I am hoping to reduce the 'on' current to much below 1 mA with the slower clock.

I have to accurately measure the frequency/rate of some events so RC oscillators are out of the question during the measure phase.

I will have ICSP programming brought out to a 6 pin header. I can load different code for the logging phase and for the data dump phase. The ICSP has access to the configuration fuses so the XT/HS changeover should be possible. I figure to push a high level (~1 Vpp)20 MHz clock over the top of the 100 KHz xtal through this header. Real estate is ultra cramped so extra gates for a clean clock changeover are out.

BrianT

Hi Brian T,
Section 2.7 of the data sheet says you can do it, but I have had far too many beers right now to discover how . . . :)

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Originally Posted by BrianT

The processor is an 18LF4620 TQFP. It spends most of its time asleep where it draws 2.6 uA with a 4 MHz xtal. It runs at about 4 mA plus the external signal conditioners on a 4 MHz xtal. I am hoping to reduce the 'on' current to much below 1 mA with the slower clock.

I have to accurately measure the frequency/rate of some events so RC oscillators are out of the question during the measure phase.

I will have ICSP programming brought out to a 6 pin header. I can load different code for the logging phase and for the data dump phase. The ICSP has access to the configuration fuses so the XT/HS changeover should be possible. I figure to push a high level (~1 Vpp)20 MHz clock over the top of the 100 KHz xtal through this header. Real estate is ultra cramped so extra gates for a clean clock changeover are out.

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Well there ya go. Add a jumper on the header to swap OSC1 between the crystal and an external X Mhz signal source (or whatever......you've got the 4xPLL to play with) and reprogram the unit to dump the data. Done dumping, reprogram for recording. At 100khz, a bit of sloppiness on the OSC lines shouldn't hurt (I've had much uglier on a 10Mhz crystal mounted roughly 2 inches from an '877A on lines that weren't so straight, still worked).

But, in the end, I like using the internal oscillator better. 31.25khz at the slowest and you can feed the 8Mhz intosc into the 4xPLL for some high speed data dumping.

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Originally Posted by BrianT

I have to accurately measure the frequency/rate of some events so RC oscillators are out of the question during the measure phase.

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Another Approach? - The 18F4620 can be clocked by switching from an external XTAL on OSC1 and OSC2 to a 32kHz XTAL on TMR1. See section 3.3.2 of the data sheet for details (from the data sheet “This gives users the option of lower power consumption while still using a high-accuracy clock source.)

An even faster way to save battery power--without even changing the bulk of your code--is to use a different PIC! The 18F4620 was NOT designed for long battery life. At 4MHz with INTOSC, it takes 1.3mA at 3.0v. There are PIC's that will do the same speed with only .58mA draw--well under 1/2 the power draw. With careful data sheet scrutiny, you should be able to find one that runs 1MHz with even less power.

You will almost double your battery life by going from 5.0 to 2.7v.

I have a friend who runs their systems for years on one battery... he has 8 or 9 voltage regulators in the system so each circuit is individually powered, and totally shut down when not in use. Yes, it is expensive, but it is very efficient.

You are trying to cram a V8 engine into a Toyota Echo so you can enter a stock car race... but there are much easier and better ways to do it. Your multiple oscillators just seems like more work than it'd be worth, considering all of the other options available. Especially when 18F's already allow you to run an external crystal or the internal osc.