Some comments on serial comms please.
OK all you geniuses out there. I am thinking about a serial comms method using the absolute minimum component count (finished size is absolutely paramount, need to be in order of 20mm X 7mm PCB, therefore SMD and minimum component count). That said, I need some smart (read intelligent) comments on the idea I am playing with.
Master end is the clock generating end. This is also the power providing end, so a clock that idles high can be bled at the slave end to pick up Vdd, so far no probs.
The clock sequence is this: Clock idles Hi, slave bleeds Vdd from this line. This line is also fed into slave PIC as clock (or input) signal. Some milliseconds after clock goes LO, slave PIC either loads or does not load the line, depending on data 1 or 0. At same time, master PIC reads an opto to see if the LED is on (slaves 0 will load line enough to turn on LED, while 0 will not) this then becomes the bit data that the slave is sending. Master takes in this data bit and then takes clock HI and then LO again for second clock pulse and this repeats for however many bits are required to be received. Always same number (will probably do 8 bits), always with an idle High time for Vdd bleeding at slave.
To my simple way of thinking, this should work reasonably well and being sort of current loop should be reasonably noise immune over some 250 feet or so at pretty slow speed of around 1 sec between transmissions.
This can all be done with 1 x 8 pin PIC, 2 x diodes and 1 x cap for Vdd storage and will fit in the aforementioned PCB size.
I just gotta get all the timing right and play around a bit.
Any constructive comments more than welcome.
And I have/will RTFM to find the most suitable PIC for the application. (needs FF bits of EEPROM as well, so probably the 12f629)
I think all this is called Bit Banging??
Thanks in advance as usual,
Muddy0409
OK it's now 4 hours later and I'ver done a bit of writing: SEE BELOW
'************************************************* ***************
'* Name : UNTITLED.BAS *
'* Author : P. Moritz *
'* Notice : Copyright (c) 2007 P. Moritz *
'* : All Rights Reserved *
'* Date : 13/06/07 *
'* Version : 1.0 *
'* Notes : *
'* : *
'************************************************* ***************
@ DEVICE pic16F877, XT_OSC ' System Clock Options
@ DEVICE pic16F877, WDT_ON ' Watchdog Timer
@ DEVICE pic16F877, PWRT_ON ' Power-On Timer
@ DEVICE pic16F877, BOD_ON ' Brown-Out Detect
@ DEVICE pic16F877, LVP_OFF ' Low-Voltage Programming
@ DEVICE pic16F877, CPD_OFF ' Data Memory Code Protect
@ DEVICE pic16F877, PROTECT_OFF ' Program Code Protection
@ DEVICE pic16F877, WRT_OFF ' Flash Memory Word Enable
trisb = 0
CLK1 VAR PORTB.0 'clock pin
TRISC = 255
TICKS VAR BYTE 'bit counter
REPLY VAR BYTE 'data store
DLY CON 250 'timing delay (SOT)
high clk1 'idle clock high for Vdd to slave
pause 5000 '
LOOP:
FOR TICKS = 0 TO 7 'for bits 0 - 7 = 8 bits per message
LOW CLK1 'lo clock
PAUSE DLY 'wait delay
HIGH CLK1 'high clock again
PAUSE DLY/2 'wait half delay
REPLY[TICKS] = PORTC.0 'read data in
PAUSE DLY/2 'wait second half of delay (is this really necessary??)
'next clock pulse
NEXT TICKS
pause 5000 'idle 5 secs
'THIS IS NOT HAPPENING????????? Y NOT?????
GOTO LOOP 'repeat
To my way of thinking, this should be simple. BUT the second PAUSE 5000 is NOT bloody happening. This is the clock idle time between bursts. The comment says it all.
