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I wonder if anyone managed to work with DT-INTS18 with the K42 series chips.
The latest DT_INTS-18_K42c.bas file that tumbleweed posted (on this closed thread https://www.picbasic.co.uk/forum/sho...=interrupt+k42) never compiled for me.
The erros I get are:
[ASM ERROR] Symbol not previously defined (INT_ENTRY_H) (0) : Error[113]
[ASM ERROR] Symbol not previously defined (INT_ENTRY_L) (0) : Error[113]
Would like to use Timer 1 interrupts for housekeeping.
Ioannis
sheldon sent me these for a project i was assisting with. it all seemed to work
Thanks Richard.
Ioannis
Tried the files and indeed it worked OK. Sort off...
I tried to setup the Timer 0 as 16bit timer, cloked by Fosc/4 with system clock at 64MHz.
Reload value $C187
The toggle happens every 4 seconds instead of 1sec. Cannot see my error.
Have checked the OSCFRQ value and it read as $08.
This is the test code:
IoannisCode:'PIC18F47K42
#CONFIG
CONFIG FEXTOSC = OFF ;Oscillator not enabled
CONFIG RSTOSC = HFINTOSC_64MHZ ;HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1
CONFIG CLKOUTEN = OFF ;CLKOUT function is disabled
CONFIG PR1WAY = OFF ;PRLOCK bit can be set and cleared repeatedly
CONFIG CSWEN = ON ;Writing to NOSC and NDIV is allowed
CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
CONFIG MCLRE = INTMCLR ;If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
CONFIG PWRTS = PWRT_64 ;PWRT set at 64ms
CONFIG MVECEN = OFF ;Interrupt contoller does not use vector table to prioritze interrupts
CONFIG IVT1WAY = OFF ;IVTLOCK bit can be cleared and set repeatedly
CONFIG LPBOREN = OFF ;ULPBOR disabled
CONFIG BOREN = ON ;Brown-out Reset enabled according to SBOREN
CONFIG BORV = VBOR_245 ;Brown-out Reset Voltage (VBOR) set to 2.45V
CONFIG ZCD = OFF ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
CONFIG PPS1WAY = OFF ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
CONFIG STVREN = ON ;Stack full/underflow will cause Reset
CONFIG DEBUG = OFF ;Background debugger disabled
CONFIG XINST = OFF ;Extended Instruction Set and Indexed Addressing Mode disabled
CONFIG WDTCPS = WDTCPS_31 ;Divider ratio 1:65536; software control of WDTPS
CONFIG WDTE = SWDTEN ;WDT enabled/disabled by SWDTEN bit
CONFIG WDTCWS = WDTCWS_7 ;window always open (100%); software control; keyed access not required
CONFIG WDTCCS = LFINTOSC ;WDT reference clock is the 31.0 kHz LFINTOSC
CONFIG BBSIZE = BBSIZE_512 ;Boot Block size is 512 words
CONFIG BBEN = OFF ;Boot block disabled
CONFIG SAFEN = OFF ;SAF disabled
CONFIG WRTAPP = OFF ;Application Block not write protected
CONFIG WRTB = OFF ;Configuration registers (300000-30000Bh) not write-protected
CONFIG WRTC = OFF ;Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ;Data EEPROM not write-protected
CONFIG WRTSAF = OFF ;SAF not Write Protected
CONFIG LVP = OFF ;HV on MCLR/VPP must be used for programming
CONFIG CP = OFF ;PFM and Data EEPROM code protection disabled
#ENDCONFIG
DEFINE OSC 64
Include "c:\users\pikst\desktop\coil\DT_INTS-18xv.bas"
Include "c:\users\pikst\desktop\coil\ReEnterPBP-18xv.bas"
'Include "c:\users\pikst\desktop\coil\ReEnterPBP-18xvLP.bas"
' Congigure I/O Digital/Analog ********************************
ANSELA = %00000011 ' RA0, RA1 analog, other PORTA digital
ANSELB = %00000000 ' PORTB digital
ANSELC = %00000000 ' PORTC digital
ANSELD = %00000000 ' PORTD digital
ANSELE = %00000000 ' PORTE digital
LATA = %00000000
LATB = %00001010
LATC = %00000000
LATD = %00000000
LATE = %00000000
TRISA = %00000011
TRISB = %00000000
TRISC = %00110000
TRISD = %00000000
TRISE = %00000000
;*********************************************************************
; ADC Settings
;*********************************************************************
Define ADC_BITS 12 ' Set number of bits in result
Define ADC_SAMPLEUS 50 ' Set sampling time in uS
ADCON0 = %00010100 ' ADC clock = internal RC, right-justify ADC results in ADRES
'ADCON1=%10110000
'ADCON2=%00000000
'*************************************************************
' Timer0 Setup
'*************************************************************
T0CON0=%00010000 'Timer 0 set as 16bit timer
T0CON1=%01000000 'Timer 0 clock source Fosc/4
Timer0 var T0CON0.7'Timer Enable bit
TMR0L=$80 'Load Timer 0 with start value $C180
TMR0H=$C1 'to count up 16000 steps until rollover
'Timer0 Setup end ********************************************
adval Var word ' Create adval to store result
temp var word
temp1 var word
tempb var byte
seconds var word
goto over_ISR
Timer0_ISR: 'Timer 0 overflow interrupt every 1msec
if seconds<1000 then
seconds=seconds+1
else
seconds=0
Timer0=0 'Stop timer0
TMR0L=$87 'Load Timer 0 with start value $C187
TMR0H=$C1 'to count up 16000 steps until rollover
Timer0=1 'Start timer0
toggle portc.5
endif
@ INT_RETURN
over_ISR:
pause 500
':::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
ASM
INT_LIST macro ; IntSource, Label, Type, ResetFlag?
INT_Handler TMR0_INT, _Timer0_ISR, PBP, yes
endm
INT_CREATE
ENDASM
@ INT_ENABLE TMR0_INT
Timer0=1 'start timer 0
mainloop:
pause 500
Goto mainloop ' Do it forever
end
looks like not reloading the tmr count every ms....... after first int, tmr counter looping from 0 .....???
Two things...
Since you're using FOSC/4 as the source, set ASYNC bit in T0CON1.
Also, when using 16 bit mode (MD16=1) you should always write TMR0H then TMR0L in that order so that the high byte is latched.
Sure it is. Inside the ISR, Timer 0 is stopped, reloaded and restarted.Quote:
Originally Posted by amgen
I think is it obligatory to use Fosc/4. Unless I misunderstood the DS. Then why is it necessary to use ASYNC=1? Could not fine any notes on the DS.Quote:
Originally Posted by tumbleweed
Same for TMR0H. Is it in the DS this?
Thank you for the suggestions, will test them the soonest.
Ioannis
The SYNC block uses FOSC/4 as its sync clock, so it's difficult to use it if it's using FOSC/4 as its input source for counting too.
Attachment 9966
for 16-bit read/write see sec 20.1.1.1:
Attachment 9965
In 16-bit mode the operations should be: write TMR0H, TMR0L and read TMR0L, TMR0H
Thanks for the explanation.
I misinterpreted these paragraphs. My understanding was to have ASYNC cleared and use Fosc/4.
Ioannis