Direct Port Manipulation PBP3 Pro silver edition

Hello everyone,

I currently have the PBP3 silver edition, on this edition I can use a PIC18F25K22 with an internal clock of 64Mhz max.

my question is how fast can I send a signal either a pulse or a High to Low / Low to high to any I/O port.

I'm looking to send a signal with a duration less than 1us (around 100ns ~ 800ns) in that range

Is it possible with PBP3 Basic instructions.

Thanks for any comments.

Re: Direct Port Manipulation PBP3 Pro silver edition

At 64MHz each instruction cycle is 62.5ns so

Code:

LATB.0 = 1 @ NOP LATB.0 = 0

Will produce a 125ns pulse. Remove the @NOP for 62.5ns

Re: Direct Port Manipulation PBP3 Pro silver edition

I think Richard noted that it is not good idea to manipulate LAT registers.

Maybe I am wrong though,

Ioannis

Re: Direct Port Manipulation PBP3 Pro silver edition

Quote:

Maybe I am wrong though,

indeed you are

this is correct code
LATB.0 = 1
@ NOP
LATB.0 = 0

this is incorrect [pbp high level commands cannot be used with LATx registers]
HIGH LATB.0
@ NOP
LOW LATB.0

Re: Direct Port Manipulation PBP3 Pro silver edition

Thanks for great help

I understand the NOP , but the LATB.0 = 1 ?

Where can I find information about LAT command/function and NOP

I assume this LAT = register
B = Port
.0 = Pin#
1/0 = High or Low

I'll test this code below and post the oscilloscope results
If someone can verify my code it it's correct for a 64Mhz clock speed.
used meConfig to generate the config section.
Thanks again

Code:

' PIC18F25K22 ' Name : Pulse Test ' Date : Oct 25-2024 '********************************************************************** ;----[18F25K22 Hardware Configuration]------------------------------------------ #CONFIG CONFIG FOSC = HSHP ; HS oscillator (high power > 16 MHz) CONFIG PLLCFG = ON ; Oscillator multiplied by 4 CONFIG PRICLKEN = OFF ; Primary clock can be disabled by software CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled CONFIG IESO = OFF ; Oscillator Switchover mode disabled CONFIG PWRTEN = OFF ; Power up timer disabled CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG BORV = 190 ; VBOR set to 1.90 V nominal CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect CONFIG WDTPS = 32768 ; 1:32768 CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1 CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset CONFIG CCP3MX = PORTB5 ; P3A/CCP3 input/output is multiplexed with RB5 CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status CONFIG T3CMX = PORTC0 ; T3CKI is on RC0 CONFIG P2BMX = PORTB5 ; P2B is on RB5 CONFIG MCLRE = INTMCLR ; RE3 input pin enabled; MCLR disabled CONFIG STVREN = ON ; Stack full/underflow will cause Reset CONFIG LVP = OFF ; Single-Supply ICSP disabled CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) CONFIG DEBUG = OFF ; Disabled CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) not code-protected CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) not code-protected CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected CONFIG CPD = OFF ; Data EEPROM not code-protected CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) not write-protected CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) not write-protected CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ; Data EEPROM not write-protected CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks #ENDCONFIG DEFINE OSC 64 ANSELA = 0 TRISA = %000000 OSCTUNE = $40 OSCCON = $70 do LATA.0 = 1 @ NOP @ NOP LATA.1 = 0 @ NOP LATA.1 = 1 @ NOP @ NOP LATA.0 = 0 PAUSE 1000 LOOP END

1 Attachment(s)

Re: Direct Port Manipulation PBP3 Pro silver edition

Hello

I'm not sure if my code are alright I programmed a PIC18F25K22

and put 2 oscilloscope probe on Pin RA0, and RA1 as form the code listed and no signal found on those 2 pins.

I use this chip to control other logic chips, and 2 of theses pin need to send 1 pulse each as shown in the scope pic.

I'm missing some info's

If possible let me know what I'm doing wrong with my code.

thank you

Attachment 9800

Code:

' PIC18F25K22 28x2 ' Name : Pulse Test ' Date : Oct 25-2024 '********************************************************************** ;----[18F25K22 Hardware Configuration]------------------------------------------ #CONFIG CONFIG FOSC = HSHP ; HS oscillator (high power > 16 MHz) CONFIG PLLCFG = ON ; Oscillator multiplied by 4 CONFIG PRICLKEN = OFF ; Primary clock can be disabled by software CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled CONFIG IESO = OFF ; Oscillator Switchover mode disabled CONFIG PWRTEN = OFF ; Power up timer disabled CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG BORV = 190 ; VBOR set to 1.90 V nominal CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect CONFIG WDTPS = 32768 ; 1:32768 CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1 CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset CONFIG CCP3MX = PORTB5 ; P3A/CCP3 input/output is multiplexed with RB5 CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status CONFIG T3CMX = PORTC0 ; T3CKI is on RC0 CONFIG P2BMX = PORTB5 ; P2B is on RB5 CONFIG MCLRE = INTMCLR ; RE3 input pin enabled; MCLR disabled CONFIG STVREN = ON ; Stack full/underflow will cause Reset CONFIG LVP = OFF ; Single-Supply ICSP disabled CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) CONFIG DEBUG = OFF ; Disabled CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) not code-protected CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) not code-protected CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected CONFIG CPD = OFF ; Data EEPROM not code-protected CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) not write-protected CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) not write-protected CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ; Data EEPROM not write-protected CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks #ENDCONFIG DEFINE OSC 64 ANSELA = 0 TRISA = 0000 OSCTUNE = $40 OSCCON = $70 do LATA.0 = 1 @ NOP @ NOP LATA.1 = 0 @ NOP LATA.1 = 1 @ NOP @ NOP LATA.0 = 0 LOOP END

1 Attachment(s)

Re: Direct Port Manipulation PBP3 Pro silver edition

Hello everyone,

I have good news !

it's finally work fine let me explain my mistakes.

Changed :
CONFIG FOSC = HSHP ; HS oscillator (high power > 16 MHz) (need External Xtal)

for :
CONFIG FOSC = INTIO67 ; Internal oscillator block (Internal OSC)

and all the pin signals shows up on the scope.

I like to thanks everyone here for your excellent support, and also Charles Leo from MELabs.

Just one more question about the LAT and @ NOP instruction I'm not familiar with theses instructions where can I find
documentations, and does it work with all PIC or just for a family of PIC like this one PIC18F25K22.

Here's the scope results with 2 set of code.

Attachment 9801

Re: Direct Port Manipulation PBP3 Pro silver edition

LATB is a register within the PIC, not a PBP command. Exactly the same as TRISA, CMCON, WPUA, ANSELA, ADCON and a few hundred more that you will not find in the PBP manual but rather in the datasheet for the specific PIC you're using - again because they are not PBP commands but registers in the PIC that you can read/write.

LATB.0 = 1 is the syntax used to set bit 0 of the LATB register to '1'.

Not all PICs have a LAT registers. On those who don't you need use the PORT register instead.

NOP is the assembly instruction "No Operation" which "wastes" one instruction cycle. @ is the inline assembly directive used to tell PBP that the rest of the line is in fact assembly and not PBP commands.

Re: Direct Port Manipulation PBP3 Pro silver edition

Quote:

Originally Posted by HenrikOlsson

LATB is a register within the PIC, not a PBP command. Exactly the same as TRISA, CMCON, WPUA, ANSELA, ADCON and a few hundred more that you will not find in the PBP manual but rather in the datasheet for the specific PIC you're using - again because they are not PBP commands but registers in the PIC that you can read/write.

LATB.0 = 1 is the syntax used to set bit 0 of the LATB register to '1'.

Not all PICs have a LAT registers. On those who don't you need use the PORT register instead.

NOP is the assembly instruction "No Operation" which "wastes" one instruction cycle. @ is the inline assembly directive used to tell PBP that the rest of the line is in fact assembly and not PBP commands.

Thanks so much HenrikOlsson for all this,
just read about (LAT register (output latch)) in datasheet, and found the NOP but was puzzle about the @. you did clarify all this.