Replacing 16F628A with 16F1827 - need help, please !

Hi all !
I have a montage where I use 16F628A I/P with the settings below. Due to the price that has increased a lot and the unavailability (is it an older generation?) I would like to switch to 16F1827 (or 16F1826), which has the same number and arrangement of ports. I don't use ADC at all !
Can somebody help me with some advice, what exactly should I change in the uC setting part? I looked in the datasheet, but it is (much too) complex for my level...
Thank you in advance for any answer !

On port A 2,3,4 I read if level is high or low, on port B (all) I run 0 or 1 logic according to levels on port A. That's all !

Code:

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@ __config _INTOSC_OSC_NOCLKOUT & _WDT_OFF & _PWRTE_ON & _MCLRE_ON & _BODEN_ON & _LVP_OFF & _CP_OFF

include "alldigital.pbp"
  DEFINE  OSC 4          ' 4MHz
  CMCON = 7                ' Disable on-chip comparator, PORTA in digital mode


TRISA = %00011100         
PORTA = %00011100
PORTB = %00000000
TRISB = %11111111

OPTION_REG.7 = 1

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Here are my settings. Use it as a starting point.

Code:

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#config
  __config _CONFIG1, _FOSC_INTOSC & _WDTE_ON & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_ON & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
  __config _CONFIG2, _WRT_OFF & _PLLEN_OFF & _LVP_OFF & _STVREN_OFF ;& _BORV_25
#endconfig

DEFINe OSC 32

DEFINE HSER_RCSTA 90h
DEFINE HSER_TXSTA 24h                                '9600 baud rate, BRGH=1
DEFINE HSER_BAUD 115200
DEFINE HSER_SPBRG 68
DEFINE HSER_CLROERR 1         

'' Set LCD Data port
'DEFINE LCD_DREG PORTB
'' Set starting Data bit (0 or 4) if 4-bit bus
'DEFINE LCD_DBIT 4
'' Set LCD Register Select port
'DEFINE LCD_RSREG PORTA
'' Set LCD Register Select bit
'DEFINE LCD_RSBIT 6
'' Set LCD Enable port
'DEFINE LCD_EREG PORTA
'' Set LCD Enable bit
'DEFINE LCD_EBIT 7
'' Set LCD bus size (4 or 8 bits)
'DEFINE LCD_BITS 4
'' Set number of lines on LCD
'DEFINE LCD_LINES 2
'' Set command delay time in us
'DEFINE LCD_COMMANDUS 2500
'' Set data delay time in us

DEFINE LCD_DATAUS 50
DEFINE ADC_BITS 10 ' Set number of bits in result (8, 10 or 12)
DEFINE ADC_CLOCK 2 ' Set clock source (FOSC/32=2, RC = 3)
DEFINE ADC_SAMPLEUS 5 ' Channel change pause in μs

OSCCON= %11110000  'PLL enabled, Internal RC-8MHz
 
while !oscstat.6 : wend

'set Pull ups on Port B
WPUB=%11111111

'set pull ups on Port A
WPUA=%00000000

PORTA = 0:PORTB=%00000000
TRISA = %00001111

TRISB = %00000000

ADCON0 = %00000000
ADCON1 = %00000000

ANSELA = %00000000          ' No analog
ANSELB = %00000000          ' RB digital

'APFCON0 = %00000000
'APFCON1 = %00000001

'BAUDCON = %00011000          'Bit 4: 1 Inverted data on Tx, 0 Non inverted

'CCP1CON = %00000000          'Control of CCPx modules
'CCP2CON = %00000000
'CCP3CON = %00000000
'CCP4CON = %00001100

CM1CON0.7=0    'Comparator 1 OFF
CM2CON0.7=0    'Comparator 2 OFF

CPSCON0 = 0    'Cap sense OFF
CPSCON1 = 0    'Cap sense OFF

DACCON0 = 0    'DAC off

FVRCON = 0  'Fixed Voltage reference OFF

OPTION_REG = %01000111  'Tmr0 from 256 presc and Int Clock

;INTEDG set for INTE interrupts
;IOCBP = %00000000          'Disable Positive edge IOC on PortB
;IOCBN = %00000111          'Enable IOC on negative edge
;INTCON = %10001000'%10001000          'Enable global interrupts and IOC

WDTCON = %00010101

INTCON = %00000000      ' Interrupt enable and INTE enable
                     
'PIR1 = 0            ' clear TMR1 int flag                   
'PIE1 = %00000001    ' TMR1 int enabled

'T1CON = %00110000    ' TMR1 1:8 prescale, timer1 off
' 
'DEFINE CCP4_REG PORTA
'DEFINE CCP1_BIT 4   
'DEFINE CCP2_REG PORTB
'DEFINE CCP2_BIT 6

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Ioannis

Thank you ! Just tried ... What could cause these two errors?

It looks like you have a 16F1826 selected instead of 16F1827.

Those errors comes from using the wrong syntax for the CONFIG block. The example Ioannis posted compiles just fine.

Yes, the Config block generated errors.
Solved by writing :

Code:

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ASM
  __config _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_ON & _CPD_ON & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_ON & _FCMEN_ON
  __config _CONFIG2, _WRT_ALL & _PLLEN_ON & _STVREN_ON & _LVP_OFF & _BORV_19 &  _LVP_OFF
ENDASM

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Thank you all for your support.
I am going to check if the assembly works correctly.