Re: 18F4550 Config settings
to have clk out on osc2 pin mode cannot be any of the io modes ie ECPLLIO_EC needs to be ECPLL_EC
clk out will be fosc/4
ps
Quote:
It's been over 5 hours
time better spent knocking serial spam offenders like this on the head in my opinion
http://www.picbasic.co.uk/forum/showthread.php?t=24436
Re: 18F4550 Config settings
Thanks Richard.
I really do not care if the clock will be available on clk2 out or not. I'd rather prefer to keep that pin as an I/O. But anyway. The thing won't run. Or at least at the expected speed.
According to the PIC18F4550.INFO file, if I want to keep an I/O function on the clk2 pin, and also have PLL enabled the ECPLLIO_EC is to be used.
I wonder if the order of configs play any role. I'll check it later today.
Ioannis
p.s. I nailed the spammer!
1 Attachment(s)
Re: 18F4550 Config settings
for 4m ext clock with usb and 48m fosc i/o on a6
Code:
#CONFIG
CONFIG PLLDIV = 1 ; No prescale (4 MHz oscillator input drives PLL directly)
CONFIG CPUDIV = OSC1_PLL2 ; [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
CONFIG USBDIV = 2 ; USB clock source comes from the 96 MHz PLL divided by 2
CONFIG FOSC = ECPLLIO_EC ; EC oscillator, PLL enabled, port function on RA6 (ECPIO)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
CONFIG PWRT = OFF ; PWRT disabled
CONFIG BOR = ON ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
CONFIG BORV = 3 ; Minimum setting
CONFIG VREGEN = ON ; USB voltage regulator enabled
CONFIG WDT = ON ; WDT enabled
CONFIG WDTPS = 512 ; 1:512
CONFIG CCP2MX = ON ; CCP2 input/output is multiplexed with RC1
CONFIG PBADEN = OFF ; PORTB<4:0> pins are configured as digital I/O on Reset
CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation
CONFIG MCLRE = ON ; MCLR pin enabled; RE3 input pin disabled
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG ICPRT = OFF ; ICPORT disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) is not code-protected
CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) is not code-protected
CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) is not code-protected
CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) is not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) is not code-protected
CONFIG CPD = OFF ; Data EEPROM is not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) is not write-protected
CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) is not write-protected
CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) is not write-protected
CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) is not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) are not write-protected
CONFIG WRTB = OFF ; Boot block (000000-0007FFh) is not write-protected
CONFIG WRTD = OFF ; Data EEPROM is not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
#ENDCONFIG
Attachment 9109
good work the spammers add no value
Re: 18F4550 Config settings
This is the configuration that is making my life miserable...
Cannot understand why on earth it does not work...
Once it started at a very very low speed and that was it. Dead still since.
Ioannis
Re: 18F4550 Config settings
At last it works!
So embarrassed though... A bad connection was the problem on the breadboard. Duh!
Thanks for the time you wasted with me.
Ioannis
