CCP2 troubles with 18F4620
I have successfully used this code with an 18F2221 and it worked fine, and as far as I can tell everything is configured to work with the 18F4620 but I can not get usable results from the CCP2 input. CCP1 works fine and I'm using the same configs and pulse on both pins. It successfully interrupts but the value returned is always 65,534 regardless of the pulse length. I'm sure I'm missing a config somewhere, but could use some help finding it.
Code:
'****************************************************************
'* Version : 1.0 PIC18F4620 11/18/2015 (Works on 18F2221) *
'* Notes : proto board 1 testing *
'* : pulse input on CCP1 works fine *
'* : pulse input on CCP2 does not work, shows 65,534 *
'****************************************************************
OSCCON=%01110000 ' SET TO 8 MHZ internal oscillator
DEFINE OSC 08 ' 8MHZ clock speed
DEFINE INTHAND X_CCP_INT ' Declare interrupt handler
ADCON1 = 15 ' All digital (AN0-AN3 will be used)
CMCON = 7 ' Turns off comparators
define LCD_COMMANDUS 1500 ' set command delay in us
define LCD_DATAUS 50 ' set data delay in us
define LCD_DREG PORTD ' set LCD data port
define LCD_DBIT 4 ' set LCD starting data bit
define LCD_RSREG PORTD ' define RS port
define LCD_RSBIT 2 ' define RS bit
define LCD_EREG PORTD ' set LCD ENABLE port
define LCD_EBIT 3 ' set LCD ENABLE bit
define LCD_BITS 4 ' set LCD bits 4 or 8
define LCD_LINES 2 ' set # of LCD rows 2 or 4
Symbol Capture = PIR1.2 ' CCP1 capture flag
SYMBOL CapIE = PIE1.2 ' CCP1 interrupt enable bit
SYMBOL CapPriEn = IPR1.2 ' priority enable bit for CCP1 interrupt
SYMBOL PriEnable = RCON.7 ' set to enable priority levels on interrupts
_T1 VAR WORD BANKA SYSTEM ' 1st capture value
PW VAR WORD BANKA SYSTEM ' 2nd capture value & ultimately final pulse width
CF VAR BYTE BANKA SYSTEM ' indicates when last capture is ready
Period var word
Symbol Capture2 = PIR2.0 ' CCP2 capture flag
SYMBOL CapIE2 = PIE2.0 ' CCP2 interrupt enable bit
SYMBOL CapPriEn2 = IPR2.0 ' priority enable bit for CCP2 interrupt
_T2 VAR WORD BANKA SYSTEM ' 1st capture value
PW2 VAR WORD BANKA SYSTEM ' 2nd capture value & ultimately final pulse width
CF2 VAR BYTE BANKA SYSTEM ' indicates when last capture is ready
Period2 var word
pause 500
LCDOUT $FE,1
CLEAR ' clear RAM on POR
TRISC.2 = 1 ' CCP1 input pin (Capture1 input on 18F4620)
TRISC.1 = 1 ' CCP2 input pin (Capture2 input on 18F4620)
INTCON = 0 ' Interrupts off for now
GOTO start ' jump over interrupt handler
ASM
X_CCP_INT
BTFSC PIR1,2 ; if ccp1
BRA CCP_INT ; goto CCP_INT
BTFSC PIR2,0 ; if ccp2
BRA CCP2_INT ; goto CCP2_INT
RETFIE FAST ; outta here
CCP_INT
BTFSS CCP1CON,0 ; capture from rising edge?
BRA Fall ; no .. goto falling edge
MOVFF CCPR1L, _T1 ; get low capture byte into _T1
MOVFF CCPR1H, _T1+1 ; get high capture byte into _T1
BRA IntExit ; outta here
Fall
MOVFF CCPR1L, PW ; get low capture byte into PW
MOVFF CCPR1H, PW+1 ; get high capture byte into PW
BSF CF,0 ; indicate last capture
IntExit
BTG CCP1CON,0 ; toggle between rising/falling edge captures
BCF PIR1,2 ; clear capture interrupt flag bit
RETFIE FAST ; return/restore W, STATUS and BSR
CCP2_INT
BTFSS CCP2CON,0 ; capture from rising edge?
BRA Fall2 ; no .. goto falling edge
MOVFF CCPR2L, _T2 ; get low capture byte into _T1
MOVFF CCPR2H, _T2+1 ; get high capture byte into _T1
BRA IntExit2 ; outta here
Fall2
MOVFF CCPR2L, PW2 ; get low capture byte into PW
MOVFF CCPR2H, PW2+1 ; get high capture byte into PW
BSF CF2,0 ; indicate last capture
IntExit2
BTG CCP2CON,0 ; toggle between rising/falling edge captures
BCF PIR2,0 ; clear capture interrupt flag bit
RETFIE FAST ; return/restore W, STATUS and BSR
ENDASM
start:
'******************** CCP1 / CCP2 / Timer 1 ********************
CCP1CON = %00000110 'Capture mode, capture on 4th rising edge
CCP2CON = %00000110 'Capture mode, capture on 4th rising edge
T1CON.7=1 'Enable timer 16 bit `
T1CON.6=1 'Timer1 OSC
T1CON.5=1 '1:8 prescaler
T1CON.4=1 '1:8 prescaler
T1CON.3=0 'Timer1 OSC off
T1CON.2=0 'sychro clock
T1CON.1=0 'Internal clock
TMR1H = 0 'Clear high byte of TMR1 counter
TMR1L = 0 'Clear low byte
PriEnable = 1 'Enable priority levels on interrupts
Capture = 0 'Clear capture flag bit
Capture2 = 0 'Clear capture flag bit
CapPriEn = 1 'Set CCP1 int to high priority
CapPriEn2 = 1 'Set CCP2 int to high priority
CapIE = 1 'Enable the CCP1 capture interrupt
CapIE2 = 1 'Enable the CCP2 capture interrupt
INTCON = %11000000 'Global + peripheral ints enabled
T1CON.0 = 1 'Turn TMR1 on here
main:
IF CF.0 THEN
period = PW-_T1
CF.0 = 0
ENDIF
IF CF2.0 THEN
period2 = PW2-_T2
CF2.0 = 0
ENDIF
lcdout $fe, $80, "CCP1= ", dec5 period
lcdout $fe, $C0, "CCP2= ", dec5 period2
goto main
end
Re: CCP2 troubles with 18F4620
Sorry to reply to my own thread. It seems to me that CCP2 isn't using timer 1 like I want, but not quite sure. Even with this code which should make both CCP modules use timer 1
Code:
T3CON.6=0 'CCP1 = Timer 1
T3CON.3=0 'CCP2 = Timer 1
Re: CCP2 troubles with 18F4620
Nobody? I can't get CCP2 to work even by itself. Possible chip or datasheet error?
