PICs interrupts - I don't clearly understand the DS's "vocabulary"

Hello,

I need some clarification about the interrupts's vocabulary used in the datasheets - still don't understand all of this sometimes strange language :p

What exactly are or what is the difference between:

1.- "unmasked" interrupts?

2.- "unmasked peripheral" interrupts?

3.- "external" interrupts?

4.- "change" interrupts?

1.- "unmasked" interrupts?
This would be ANY interrupt that has its enable bit set.

2.- "unmasked peripheral" interrupts?
This would be an "enabled" interrupt that comes from any of the peripherals (timers, usart, ADC, MSSP etc)

3.- "external" interrupts?
This would be INT0, INT1 etc

4.- "change" interrupts?
This would be the Interrupt on change feature normally available on PortB.4-7

The interrupt flag for each available interrupt is always set when the "event" happends (timer overflows, byte comes in on the USART etc). But if the interrupt isn't "enabled" the interrupt flag won't actually cause an interrupt - the interrupt is masked.

/Henrik.

Thanks a lot Henrik,

That is just as clear as crystal!

I dream data-sheets could be as clear as your explanation ;)

Thanks again and have a nice day.

Quote:

---

Originally Posted by HenrikOlsson

3.- "external" interrupts?
This would be INT0, INT1 etc

---

Henrik,

Thank you for clarifying these concepts for many of us. Now, isn't INT0 and INT1 internally available in the chips? Do you mean by "External" that you are feeding an external clock signal to INT0 and INT1?

Robert

Hi,
Not exactly sure what you mean. I guess you can trip the INT0 interrupt "internally" simply by setting the interrupt flag so in that sense they are available internally. But what is meant by external is that the event causing the interrupt is being external to the PIC itself, ie an event on the physical pin. In the case if INT0 (which is usually on PortB.0) either a rising a falling edge depending on how it's setup.

/Henrik.

One more question please,

What does this mean?
Attachment 5775
Shall it mean, that in XT, HS and LP Oscillator modes, no level change (from 1 to 0) will ever be seen by the PIC?

I would bet those pins are assign to those you connect the Crystal to... so they're no longer regular I/O... I'm I right copain d'outre-mer?

Even Crystals have sometimes opaque zones....:D

Et bien le bonjour aux amis du pays du sirop d'érable ;)