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Dear Friends,
I Use the 16f877 to many years and now I need more memory then I want to migrate for the 18f4620.
my initial header this like this:
@ device pic16F877,HS_OSC, wdt_on, pwrt_on, bod_on, lvp_off, protect_on,wrt_off
with oscillator of 20mhz external and all PORTA and PORTE as digital
it would like the friends to help with the header of the 18f4620 so that it is the definitions same to the of the 877.
in advance thankful,
Vicente.
Hi Vicente,
@ device pic16F877,HS_OSC, wdt_on, pwrt_on, bod_on, lvp_off, protect_on,wrt_off
Is a config for use with the PM (default) assembler, which you cannot use on the 18F series of pics, so you must switch up to using MPASM. First thing you must do is tell Micro Code studio about that Click File..view..compile & assembler..assembler and install a check in the checkbox use mpasm . . . .
then you need to comment out the default config in the 18F4620.inc file located in your PBP root directory, you might just as well do a copy paste of it into your MCS code page for your first 18F project (it makes a great exemplar) and then modify it from there. Some of these are quite involved. If you open up the P18F4620.inc file located in the MPASM Suite you will see every available config and register this chip has .
Ok here are the default configs from my pbp 18F4620.inc file. I show them "commented out" by adding ; just before them.
and you would install them this way:Code:;__CONFIG _CONFIG1H, _OSC_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
;__CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
;__CONFIG _CONFIG3H, _CCP2MX_PORTC_3H & _PBADEN_OFF_3H & _LPT1OSC_OFF_3H & _MCLRE_ON_3H
;__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L
Just as with your original config adding the @ symbol tells PBP to ignore the config as it is an assembler instruction and not meant for PBP to act upon it.Code:@ __CONFIG _CONFIG1H, _OSC_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
@ __CONFIG _CONFIG2L, _BOREN_ON_2L
@ __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
@ __CONFIG _CONFIG3H, _CCP2MX_PORTC_3H & _PBADEN_OFF_3H & _LPT1OSC_OFF_3H & _MCLRE_ON_3H
@ __CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L
And you need to make them reflect what you want . .
Here are the choices from the P18F4620 file
And here is pretty much what you want . . .Code:; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0' ; LP oscillator
_OSC_XT_1H EQU H'F1' ; XT oscillator
_OSC_HS_1H EQU H'F2' ; HS oscillator
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6
_OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
_OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6
_OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7
_OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_0_2L EQU H'E7' ; Maximum setting
_BORV_1_2L EQU H'EF' ;
_BORV_2_2L EQU H'F7' ;
_BORV_3_2L EQU H'FF' ; Minimum setting
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
_WDT_ON_2H EQU H'FF' ; WDT enabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3
_CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1
_PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset
_PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation
_MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected
_CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected
_CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected
_CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected
_CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected
_CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected
_CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected
_CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected
_CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected
_CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected
_CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected
_WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected
_WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected
_WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected
_WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected
_WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected
_WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected
_WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected
;----- CONFIG6H Options --------------------------------------------------
_WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected
_WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected
_WRTB_ON_6H EQU H'BF' ; Boot Block (000000-0007FFh) write-protected
_WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-0007FFh) not write-protected
_WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks
_EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
_EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks
_EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
_EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
_EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
_EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
_EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks
_EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
;----- DEVID Equates --------------------------------------------------
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
;----- IDLOC Equates --------------------------------------------------
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
Take Notice: the configs have numbers which align with the config lines I. E. _CONFIG2H, _WDT_ON_2H notice how CONFIG2H goes with _WDT_ON_2HCode:@ __CONFIG _CONFIG1H, _OSC_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
@ __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
@ __CONFIG _CONFIG3H, _CCP2MX_PORTC_3H & _PBADEN_ON_3H & _LPT1OSC_OFF_3H & _MCLRE_ON_3H
@ __CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L
@ __CONFIG _CONFIG6L, _WRT0_OFF_6L &_WRT1_OFF_6L &_WRT2_OFF_6L & _WRT3_OFF_6L
thank you very much Archangel
helped a lot