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12.1.2.3 Receive Interrupt
The RCIF interrupt flag bit of the PIR1 register is set twhenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the INTCON register
• GIE global interrupt enable bit of the INTCON register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.