PIC18 timer0 interrupt handler, still not getting it

I tried to get this working a year ago but had trouble and gave up, just polling the TMR0 interrupt flag. But I think I really need the interrupt handler this time, and although I have looked at the Forum's answers, I'm still not getting it. I see that my init code is being called as I'm getting the two LATF.7 pulses but apparently I'm not getting the TMR0 interrupt as I get no more LATF.7 pulses. My other code is running, so I know my code is not hung somewhere. Can anyone help? Thanks!!!

The OSC is set for 40MHz and I'm telling PIC BASIC PRO about the interrupt handler with the DEFINE:
DEFINE INTLHAND pllInt

Here's my setup, called from my main program. Following the setup is the handler.
Is there anything else I need to do to get the interrupts to work?

'
PLL_SETUP:
RCV_CLK_BIT = 0
TP_RCV_CLK = 0
TP_RCV_CLK = 1
TP_RCV_CLK = 0
TP_RCV_CLK = 1
TP_RCV_CLK = 0
'SET_25US_TIMEOUT: ' set timer0 for 25us timeout, 40MHz clock
T0CON = %00001000 ' Internal clock, no prescale, Timer0 off for now
TMR0H = $FF ' Timer0 low & high bytes set for 65286, 25us
TMR0L = $06
'
ASM
;MOVLW B'11000111'
MOVLW B'10001000' ; TMR0 on, 16-bit, no prescaler
MOVWF T0CON
BCF RCON,IPEN ; disable priority interrupts
BCF INTCON,TMR0IF ; clear TMR0IF
BSF INTCON,TMR0IE ; enable TMR0 interrupt
BSF INTCON,PEIE ; peripheral interrupts enabled
BSF INTCON,GIE ; global interrupts enabled
ENDASM
RETURN

ASM
pllInt
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
;btfsc _RCV_CLK_BIT ; if RCV_CLK_BIT is clr, set it and TP_RCV_CLK
;goto clr_RCV_CLK_BIT ; RCV_CLK_BIT is set, so clear it and TP_RCV_CLK
;bsf _RCV_CLK_BIT
;;bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
;goto continue
;clr_RCV_CLK_BIT
;bcf _RCV_CLK_BIT
;bcf _TP_RCV_CLK ; clear TP_RCV_CLK, LATF.7, test point for rcv clock
;continue
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf INTCON, TMR0IF ; clear TMR0 interrupt flag
RETFIE FAST
ENDASM

Ah, there is some hope. It is interrupting at least once. I had missed the test point signals that occurred after 25us. So now to find out why it only interrupts a single time.

Here's my latest code:

PLL_SETUP:
RCV_CLK_BIT = 0
TP_RCV_CLK = 0
TP_RCV_CLK = 1
TP_RCV_CLK = 0
TP_RCV_CLK = 1
TP_RCV_CLK = 0
'SET_25US_TIMEOUT: ' set timer0 for 25us timeout, 40MHz clock
T0CON = %00001000 ' Internal clock, no prescale, Timer0 off for now
TMR0H = $FF ' Timer0 low & high bytes set for 65286, 25us
TMR0L = $06
'
ASM
;MOVLW B'11000111'
MOVLW B'10001000' ; TMR0 on, 16-bit, no prescaler
MOVWF T0CON
BCF RCON,IPEN ; disable priority interrupts
BCF INTCON,TMR0IF ; clear TMR0IF
BSF INTCON,TMR0IE ; enable TMR0 interrupt
BSF INTCON,PEIE ; peripheral interrupts enabled
BSF INTCON,GIE ; global interrupts enabled
ENDASM
RETURN

ASM
pllInt
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock

;btfsc _RCV_CLK_BIT ; if RCV_CLK_BIT is clr, set it and TP_RCV_CLK
;goto clr_RCV_CLK_BIT ; RCV_CLK_BIT is set, so clear it and TP_RCV_CLK
;bsf _RCV_CLK_BIT
;;bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
;goto continue
;clr_RCV_CLK_BIT
;bcf _RCV_CLK_BIT
;bcf _TP_RCV_CLK ; clear TP_RCV_CLK, LATF.7, test point for rcv clock
;continue
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bsf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf _TP_RCV_CLK ; set TP_RCV_CLK, LATF.7, test point for rcv clock
bcf INTCON, TMR0IF ; clear TMR0 interrupt flag
RETFIE FAST
ENDASM

Are you sure you are in the correct bank when you try to BCF and BSF the port? When you are setting them in the setup, PBP is tending to the banks. but when you BCF or BSF, YOU must ensure the correct bank.

PBP will leave you in bank 0, so if the LAT is not (highly likely) you are setting and clearing something else.

Interrupts are now occurring! I discovered that I was clearing the TMR0 interrupt enable elsewhere in my code. Now interrupts are occurring but at the wrong rate, 7ms between interrupts instead of 25us. Hopefully that'll be a simple fix. Sorry!

Where's the embarrassed icon when I need it? ( :$ )

We will surely need more info for that. I would still check the banks. What 18 are you using at a min. OSC settinmgs? things going on in other parts that we can't see?