Delta Sigma ADC is inverting

[selbstdual]

Dear Readers.

Currently I am using the setup whose picture is attached. This is a Delta-Sigma ADC from AN700.
According to my calculation I adjusted it to measure an area of about 10 to 80% of the resistor's
value.

Unfortunately in exactly this area there is happening nothing, there's one value all the time.
If I am rotating in the area being defined as out-of-range there a distinction is made.

What could be the problem, what to change ?

My code in PicBasicPro:




Define OSC 8

;Variables
result_l VAR BYTE BANK0 SYSTEM
counter VAR BYTE BANK0 SYSTEM
result_h VAR BYTE BANK0 SYSTEM

;Register
OPTION_REG = 0
TRISA = $01


;Interrupts
INTCON = 0
VRCON = $EC
CMCON = $06

Start:
GOSUB Value
StartV = ADCValue
Pause 10
GOSUB Value
EndV = ADCValue
IF StartV = EndV THEN
Low GreenLED
High YellowLED
ENDIF
IF StartV != EndV THEN
High GreenLED
Low YellowLED
ENDIF
GOTO Start
END


Value:
GOSUB Value2
ADCValue = result_l * 256 + result_h
RETURN


Value2:
ASM
DeltaSigA2D
clrf counter
clrf counter+1
clrf result_l
clrf result_h
movlw 0x03 ; set up for 2 analog comparators with common reference
movwf CMCON
loop
btfsc CMCON,C1OUT ; Is comparator high or low?
goto complow ; Go the low route
comphigh
nop ; necessary to keep timing even
bcf PORTA,3 ; PORTA.3 = 0
incfsz result_l,f ; bump counter
goto eat2cycles ;
incf result_h,f ;
goto endloop ;
complow
bsf PORTA,3 ; Comparator is low
nop ; necessary to keep timing even
goto eat2cycles ; same here
eat2cycles
goto endloop ; eat 2 more cycles
endloop
incfsz counter,f ; Count this lap through the loop.
goto eat5cycles ;
incf counter+1,f ;
movf counter+1,w ;
andlw 0x04 ; Are we done? (We're done when bit2 of
btfsc STATUS,Z ; the high order byte overflows to 1).
goto loop ;
goto exit
eat5cycles
goto $+1 ; more wasted time to keep the loops even
nop ;
goto loop ;
exit
movlw 0x06 ; set up for 2 analog comparators with common reference
movwf CMCON
ENDASM
RETURN


Green is on if there's movement(so values change) and yellow if there's none.

[mister_e]

i didn't look really well but this line jump in my face..

counter VAR BYTE BANK0 SYSTEM
'
'
'
'
'
'
'
DeltaSigA2D
clrf counter
clrf counter+1

counter must be a WORD

[selbstdual]

This made the solution work.

Do result_l and result_h have to be WORD variables ?

[mister_e]

nope, or i missed something obvious ;)

If it's working... leave it like this :D