MegaADY
- 5th October 2006, 11:46
Hello ! I encountered a little problem with a smartcard logger device. Here is my setup.
Smartcard reader wich is generating a variable clock speed , depending on the type of smartcard inserted. The clock speed is between 1-5 MHz. Smardcard IO line communicates asynchroniously with the reader at a baud rate according to it's clock.
The comms parity is estabilished according to smartcard's ATR.
Now, I can log some reader - card communications using HSERIN at 9600, but at some (variable) point , the data becomes unconsistent due to the loose of synchronisation, I suppose .
I was thinking about monitoring somehow the smartcard's clk and according to it estabilish the SPBRG value . But I don't know if I can monitor a 1-5 MHz clock with 16f628 which I use for testing
Anyone have any ideeas ?
Thank you for your attention
Smartcard reader wich is generating a variable clock speed , depending on the type of smartcard inserted. The clock speed is between 1-5 MHz. Smardcard IO line communicates asynchroniously with the reader at a baud rate according to it's clock.
The comms parity is estabilished according to smartcard's ATR.
Now, I can log some reader - card communications using HSERIN at 9600, but at some (variable) point , the data becomes unconsistent due to the loose of synchronisation, I suppose .
I was thinking about monitoring somehow the smartcard's clk and according to it estabilish the SPBRG value . But I don't know if I can monitor a 1-5 MHz clock with 16f628 which I use for testing
Anyone have any ideeas ?
Thank you for your attention