BUSY line technique

[Demon]

(cut and pasted from the guts of another thread)

Hi,

I'd appreciate a description of the BUSY line technique between 2 PICs please.

I am using a Master 16F628 with multiple Slave 16F628 using USART communication (HSERIN/OUT via TX/RX lines). I'd like to be able to use a BUSY line to indicate when the line is busy.

At first thought I would think that HIGH = NOT BUSY and LOW = BUSY, that way there is no power signal at the same time as communication, less risk of EMF disruption.

It is not known which Slave will be connected to the system. There might be none, or there might be several, that's why I'm looking for a flexible way of Slaves to send data.

Robert
:)

[Ron Marcus]

(cut and pasted from the guts of another thread)

Hi,

I'd appreciate a description of the BUSY line technique between 2 PICs please.

I am using a Master 16F628 with multiple Slave 16F628 using USART communication (HSERIN/OUT via TX/RX lines). I'd like to be able to use a BUSY line to indicate when the line is busy.

At first thought I would think that HIGH = NOT BUSY and LOW = BUSY, that way there is no power signal at the same time as communication, less risk of EMF disruption.

It is not known which Slave will be connected to the system. There might be none, or there might be several, that's why I'm looking for a flexible way of Slaves to send data.

Robert
:)

First of all, the EMF is usually induced by switching signals. Having a line high or low should make little difference. If it was rapidly switching states, it would produce noise. It helps your design if you use an industry accepted format for handshaking. I2C seems perfect, because the accepted states are low, or high impedance. There is a pull up resistor on the line to keep it high unless a slave or master pull it low to initiate data transfer. Look at the I2C function in PBP. This may be all you need. You may connect as many nodes to the line as you want, as long as they are in a high impedance state (input). One of these nodes taking the line low is the signal for the master to begin polling the slaves.

Hope this is helpful,
Ron

[Demon]

OK,

How does this process look:

- all PICs define BUSY LINE pin as INPUT.

- pull-up resistor on BUSY LINE.

- to transmit, a PIC checks if BUSY LINE is HIGH (available), BUSY LINE pin set LOW (busy). Pin is automatically set as OUTPUT by PBP LOW command.

- once finished transmitting, BUSY LINE pin is set HIGH (available), then sets pin as INPUT.

I figure it's going to be extemely bad luck for a 2nd PIC to see the line as available just when another PIC was in between checking the status of the line and setting it to busy.

Would a simple solution be adding a short delay and checking the status a 2nd time? Or am I worrying about something that will happen 'most likely' never.

Robert
:)

[Ron Marcus]

You don't need to change the pin to high before you make it an input. Just switch from low to input, or just flip the apropriate bit in the tris register which is alot faster.
If there is a bus conflict and two slaves pull the line low at exactly the same time, the worst that can happen is some corrupted data. Testing the line twice a few microseconds apart could help keep two slaves from sending data at exactly the same time.

[Demon]

Right, I forgot about the pull-up resistor. It will take care of pulling the line back HIGH when the pin changes to input, even better, one less step.

Revised:

- all PICs define BUSY LINE pin as INPUT.

- pull-up resistor on BUSY LINE.

- to transmit, a PIC checks if BUSY LINE is HIGH (available), BUSY LINE pin set LOW (busy). Pin is automatically set as OUTPUT by PBP LOW command.

- once finished transmitting, BUSY LINE pin is set as INPUT.

- pull-up resistor pulls BUSY LINE back to HIGH (available).

Thanks Ron!

Robert
:)

[Ioannis]

I think that if the pin was low and then this pn is made input the buffer inside pic will read as low if no previous read ia made. So one must read the pin twice. If I am wrong please someone correct me.

Ioannis

[Ron Marcus]

I think that if the pin was low and then this pn is made input the buffer inside pic will read as low if no previous read ia made. So one must read the pin twice. If I am wrong please someone correct me.

Ioannis


The pull up resistors will bring the line high

[Ioannis]

Yes, the line will be high, but the buffer inside the PIC? It will be revised when the port is read again.

I 'll tey to find it in the datasheet. There was a note about this.

Ioannis

[BobK]

Hello Robert,

I am currently using the scheme of the BUSY line in two systems I have developed. However I am using a single pin serial line. What I have done is created a system with a master board and 20 slaves. I have a busy line that is normally high. When a slave has a message for the master it first checks that the busy line is not low then makes the busy line low, sends its data to the master. The slave clears the low on the busy line. The master makes the busy line low just before it receives the data. It will keep the line low until the end user acknowledges the event received. The it clears the busy line allowing new data to be sent. To prevent crashes of data, each slave must wait 10ms before sending any data. The first board waits 10ms the next 20ms and so forth. The likely hood of two signals coming at the same time is virtually nill but why take the chance. Waiting 200ms isn't going to hurt anything.

I keep all of the slaves serial pins as inputs until the SEROUT2 command is used then as soon as they are finished sending I make the pin and input again.

All of the slaves are plugged into a card cage backplane so I'm not running cables all over.
In one system I am using a 16F877A for the master and 16F872 for slaves. In the other system, a 18F452 is the master (needed more memory) and the slaves are 16F74's. One system has more things to do than the other.

Hope this helps you out.

BobK