PIC 18F46K22 Wierdness

[keithdoxey]

Hi All,

Just spent over three hours trying to find a bug which doesn't appear to be a bug !!!

I have a couple of include files that I found through this forum that are used to bitbang data to some Neo Pixels on Port B.5 and it works as it should.

I have another routine that I wrote to send data to some APA102 LEDs and that also work on the PIC that I tested it on and on the one in my current project using Shiftout on A.6 and A.7

Heres the rub.... If I run the APA102 subroutine the NeoPixel one wont work. By commenting out various lines I proved it was the Shiftout command in the APA102 routine that was breaking the NeoPixel routine.

I changed the pins used by the APA102 routine from A6/A.7 to E0 and E1 and everything works just fine.

Can anyone offer a suggestion as to why that should be given that the two were running on different ports ?

[Dave]

Some port configuration data and DEFINES would be of help.

[keithdoxey]

Lots of variables cut out but the config and pin aliases for the relevant pins are shown



;----[18F46K22 Hardware Configuration]------------------------------------------
#IF __PROCESSOR__ = "18F46K22"
#DEFINE MCU_FOUND 1
#CONFIG
CONFIG FOSC = INTIO67 ; Internal oscillator block
CONFIG PLLCFG = ON ; Oscillator multiplied by 4
CONFIG PRICLKEN = OFF ; Primary clock can be disabled by software
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
CONFIG PWRTEN = OFF ; Power up timer disabled
CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
CONFIG BORV = 190 ; VBOR set to 1.90 V nominal
CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect
CONFIG WDTPS = 32768 ; 1:32768
CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1
CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset
CONFIG CCP3MX = PORTB5 ; P3A/CCP3 input/output is multiplexed with RB5
CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status
CONFIG T3CMX = PORTC0 ; T3CKI is on RC0
CONFIG P2BMX = PORTD2 ; P2B is on RD2
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Disabled
CONFIG CP0 = OFF ; Block 0 (000800-003FFFh) not code-protected
CONFIG CP1 = OFF ; Block 1 (004000-007FFFh) not code-protected
CONFIG CP2 = OFF ; Block 2 (008000-00BFFFh) not code-protected
CONFIG CP3 = OFF ; Block 3 (00C000-00FFFFh) not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD = OFF ; Data EEPROM not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-003FFFh) not write-protected
CONFIG WRT1 = OFF ; Block 1 (004000-007FFFh) not write-protected
CONFIG WRT2 = OFF ; Block 2 (008000-00BFFFh) not write-protected
CONFIG WRT3 = OFF ; Block 3 (00C000-00FFFFh) not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ; Data EEPROM not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
CONFIG EBTR3 = OFF ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG

#ENDIF

;----[Verify Configs have been specified for Selected Processor]----------------
; Note: Only include this routine once, after all #CONFIG blocks
#IFNDEF MCU_FOUND
#ERROR "No CONFIGs found for [" + __PROCESSOR__ +"]"
#ENDIF


DEFINE OSC 64 ' Int Osc (16MHz + 4*PLL)
DEFINE ADC_BITS 8 ' Set number of bits
DEFINE ADC_CLOCK 3 ' Set clock source
DEFINE ADC_SAMPLEUS 50 ' Set sampling time
'DEFINE HSER_SPBRG 9 ' 250 KBaud
define HSER_BAUD 9600
DEFINE HSER_CLROERR 1 ' Clear overflow automatically
define SHIFT_PAUSEUS 50 ' Speed of shiftout

' **** Define LCD Config ****
DEFINE LCD_DREG PORTD ' LCD is connected to Port D
DEFINE LCD_BITS 4 ' 4 bit mode
DEFINE LCD_DBIT 4 ' Connected to D.4-D.7
DEFINE LCD_RSREG PORTC ' RS pin is on Port C
DEFINE LCD_RSBIT 4 ' RS = C.4
DEFINE LCD_EREG PORTC ' Enable on Port C
DEFINE LCD_EBIT 2 ' Enable = C.2
DEFINE LCD_COMMANDUS 2000 'Command delay time in us
DEFINE LCD_DATAUS 200 'Data delay time in us

INCLUDE "DT_INTS-18.bas" ; Base Interrupt System
INCLUDE "ReEnterPBP-18.bas" ; Include if using PBP interrupts
INCLUDE "Elapsed_INT-18.bas" ; Elapsed Timer Routines


OSCCON = %01111000 ' Set to 16MHz Internal Oscillator
OSCCON2 = %10000100
OSCTUNE = %01000000

TRISA = %00001111
TRISB = %11011111
TRISC = %11000000
TRISD = %00000000
TRISE = %00000000

PORTA = %00000000
PORTB = %00000000
PORTC = %00000000
PORTD = %00000000
PORTE = %00000000


ANSELA = %00001111 ' AN0-AN3 enabled as Analog Inputs
ANSELB = %00000000 ' Disable Analog Inputs
ANSELC = %00000000 ' Disable Analog Inputs
ANSELD = %00000000 ' Disable Analog Inputs
ANSELE = %00000000 ' Disable Analog Inputs

ADCON0= %11000000
ADCON1= %00000000
ADCON2= %00000110
CM1CON0= %00000000


NeoPin var LATB.5 'NeoPixel Pin
APAData var LATE.1
APAClock var LATE.0

It works with APAData and APAClock on Port E but when they are on LATA.7 and LATA.6 then NeoPin stops working

[richard]

can't help but notice your apa pin aliases are of the latx.y type


APAData var LATE.1
APAClock var LATE.0

that is a definite no no for shiftout command

but you post no relevant info about the routine so its just a guess

gigo

[Dave]

Richard is right. you should use the PORT.X designation when defining pins to be used with SHIFTOUT or SHIFTIN.

APAData var PORTE.1
APAClock var PORTE.0

[keithdoxey]

Thanks guys, I will try with the PortX.y version instead of LATX.y although what I don't understand is why it works with the LAT commands but only stops something on Port B from working when I am using the LATA.

I chose to use LAT instead of Port as I read somewhere that on chips with Latch registers you should use those to avoid Read/Modify/Write issues.

Will report back on my findings after I retest tomorrow evening.

[HenrikOlsson]

I believe it's basically the same issue as Ioannis had the other day when he tried to use HIGH/LOW on anything but a PORT register.

Any command that automatically makes the pin in question and input or output (ie clears or sets the TRIS registers for you) must to use PORTx.y
This is because the compiler uses a hardcoded "offset" to get from the PORT register to the TRIS register.

On the 18F46K22 this "offset" between any of the PORT registers and their corresponding TRIS registers is 18 so if, for example, you use LATA.0 instead of PORTA.0 as your SHIFTOUT pin the result will be that the compiler clears OSCTUNE.0 instead of TRISA.0.

/Henrik.

[keithdoxey]

Many thanks to Richard and Dave for letting me know I should be using PORT instead of LAT and thanks to Henrik for the explanation.

Making the changes has fixed the issue and also cured a couple of other bits of randomness that were also happening.

Upto this point the program has basically been proof of concept hence why various subroutines we prototyped on another PIC before being inserted into the main code. Time now to do an upto date printout and get the highlighter pens out to note all the changes I need to make to get my program tidied up and working the way I want it to.

Thanks again guys.