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Norbert
- 24th August 2016, 15:28
Looking to get a bit more speed out of an pre-existing circuit that uses a 16F873a (max 20MHz clock), did a search for faster pin-compatible or almost pin-compatible 28-pin 16F's. Decided on the 16F1782 (32MHz internal) and put it in the circuit.
But because of an error in my initial configuration, I discovered an undocumented mode: 80MHz clock from 20MHz external osc input on RA7/CLKIN, using the configuration below.



#CONFIG
__config _CONFIG1, _FOSC_HS & _CLKOUTEN_OFF & _WDTE_ON ;so using an external osc source, but also x4 PLL (OSCCON.7 =1)
__config _CONFIG2, _PLLEN_OFF
#ENDCONFIG

DEFINE OSC 20 'defines clock frequency = 20MHz, but since actually clocking at 80MHz, a lot of the PBP timing will be off by factor 4.

WDTCON = %00011010 '8 second watchdog
OSCCON = %11111000 'PLL x 4,
INTCON = 0 'disable interrupts,
ADCON0.0 = 0 'disables a-d converter
ANSELA = 0
ANSELB = 0
INLVLA = %00001111

DACCON0.7 = 0 ' Disable DAC
CM1CON0.7 = 0 ' Disable comparator 1
CM2CON0.7 = 0 ' Disable comparator 2
CM3CON0.7 = 0 ' Disable comparator 3

TRISA = %11011111
TRISB = %11100000
TRISC = %11110000


The x4 PLL is deriving the clock from the 20MHz external osc.
Obviously, this is overclocking and outside the design specification envelope. So not for production designs without extensive reputability, reliabilty, temperature range tolerance, lifetime endurance, EMI, etc. testing.
But good for hobby projects where you need a bit more speed from a 28-pin 16F!
It runs cool to the touch, so not an exorbitant current drain, but I have not measured the current drawn.
I have only used it in an pre-existing circuit that had an external 20MHz clock, not with a 20MHz HS crystal directly on the 16F1782. But that would probably work too. Have not tried it with sleep modes either.
Runs with 5V supply, have not tried with 3V, which would probably be more critical.

Dave
- 25th August 2016, 11:49
I have a few projects that I needed some more speed for using the 16F1825 and have used a 10 Mhz. resonator with 4xPLL. I haven't seen any problems as of yet. Although not to the extent you are proposing....

CuriousOne
- 30th August 2016, 09:16
Can be same approach applied to other chips from 16F series, that support extosc ?
Say 16F1829 ?

Dave
- 30th August 2016, 12:03
I can't say for sure, so try it? There is quite a difference between what I was trying to do (40 Mhz from 32 Mhz. processor) and what you are proposing (80 Mhz. from 32 Mhz. processor).

Art
- 31st August 2016, 11:11
Nice :D What is it doing?
I wonder how on-chip EEPROM or program memory writes go.. if supported by the chip.

Norbert
- 1st September 2016, 01:16
It's only doing a simple repetitive task - triggered on dig ip by comparators, dig ops driving at any one time one of several hard pull-up transistors in a multiple 1-wire master circuit, with retrigger (blocking) timers. It's basically doing something that could be handled quicker by a few logic gates. The 1-wire communication proper (and everything else) is handled by another on-board µC - of the 18F family.
So the 16F1782 is not writing to EEPROM etc. I'll leave that interesting experiment @80MHz to someone else!

Dave
- 1st September 2016, 11:33
The program's I have written for the 16F1825 running at 40Mhz. (10 mHZ. 4 x PLL) work just fine writing and reading from eeprom. No issues.