Low power sleep mode 18f46k80

[longpole001]

Hi guys trying to get the PIC to go to sleep in the lowest power mode available

but i notice even in sleep mode i am still pulling 3ma

also that the outputs with week pullups are still active on outputs
wondering if this normal even when in sleep mode
or have missed a setting

cheers

Sheldon




' config for 18F46K80

#CONFIG

;----- CONFIG1L Options --------------------------------------------------
CONFIG XINST = OFF
CONFIG SOSCSEL = DIG ; Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled
CONFIG INTOSCSEL = HIGH ; LF-INTOSC in High-power mode during Sleep
CONFIG RETEN = ON ; regulator is Enabled (Controlled by SRETEN bit)when in sleep

;----- CONFIG1H Options --------------------------------------------------
CONFIG IESO = OFF
CONFIG FCMEN = OFF
CONFIG PLLCFG = ON
CONFIG FOSC = INTIO2 ; Internal RC oscillator , PORTA.6 , PORTA.7 as I/O

;----- CONFIG2L Options --------------------------------------------------
CONFIG BORPWR = ZPBORMV ; ZPBORMV instead of BORMV is selected
CONFIG BORV = 2 ; 2V
CONFIG BOREN = SBORDIS ; Enabled in hardware, SBOREN disabled
CONFIG PWRTEN = OFF

;----- CONFIG2H Options --------------------------------------------------
CONFIG WDTPS = 512 ; 1:512
CONFIG WDTEN = OFF ; WDT off

;----- CONFIG3L Options --------------------------------------------------
; no register in the device

;----- CONFIG3H Options --------------------------------------------------
CONFIG MCLRE = ON ; MCLR ENabled FOR DIAG , RG5 DISabled
CONFIG MSSPMSK = MSK7 ; 7 Bit address masking mode
CONFIG CANMX = PORTB ; ECAN TX and RX pins are located on RB2 and RB3, respectively

;----- CONFIG4L Options --------------------------------------------------
CONFIG BBSIZ = BB1K ; 1K word Boot Block size
CONFIG STVREN = ON

;----- CONFIG5L Options --------------------------------------------------

CONFIG CP0 = ON ; MEMORY BLOCK 0 CODE PROTECT BIT - 7KW 800h - 3FFFh ( when 1K BOOT OPTION used )
CONFIG CP1 = ON ; MEMORY BLOCK 1 CODE PROTECT BIT - 8KW 4000h - 7FFFh
CONFIG CP2 = ON ; MEMORY BLOCK 2 CODE PROTECT BIT - 8KW 8000h - BFFFh
CONFIG CP3 = ON ; MEMORY BLOCK 3 CODE PROTECT BIT - 8KW C000h - FFFFh


;----- CONFIG5H Options --------------------------------------------------
CONFIG CPD = OFF ; EEPROM DATA PREOTECT BIT - EXTERNAL R/W
CONFIG CPB = ON ; BOOT BLOCK CODE PROTECT BIT

;----- CONFIG6L Options --------------------------------------------------
CONFIG WRT0 = OFF ; MEMORY BLOCK WRITE PROTECT BIT
CONFIG WRT1 = OFF
CONFIG WRT2 = OFF
CONFIG WRT3 = OFF


;----- CONFIG6H Options --------------------------------------------------
CONFIG WRTD = OFF ; EEPROM WRITE PROTECT BIT - INTERNAL AND EXTERNAL
CONFIG WRTB = ON ; BOOT BLOCK WRITE PROTECT
CONFIG WRTC = ON ; CONFIGURATION REGISTER WRITE PROTECT BIT

;----- CONFIG7L Options --------------------------------------------------
CONFIG EBTR0 = OFF ; MEMORY READ TABLE BLOCK PROTECT
CONFIG EBTR1 = OFF
CONFIG EBTR2 = OFF
CONFIG EBTR3 = OFF

;----- CONFIG7H Options --------------------------------------------------
CONFIG EBTRB = OFF ; TABLE READ PROTECT BOOT

#ENDCONFIG





' =========== Power Shutdown routine ==================
Shut_Down:

pwr_on = 1 ' PWR ON = 1 = OFF - turns off power to devices external to cpu
@ INT_DISABLE RBC_INT ; TURN OFF PortB IOC Interrupts for RX_mode - RF_IRQ pin NOT USED WHEN IR-TX
@ INT_DISABLE RX2_INT ; Turn Off USART RX Interrupts for RX_mode - RX input on USART not used when IR-TX for configuration
@ INT_DISABLE TMR0_INT ; disable Timer0 interupts and start Timer0


INTCON.1 = 0 ' CLEAR INT0 interupt flag prior to enable
PWR_shutdown = 0 ' CLEAR shutdown flag
@ INT_ENABLE INT0_INT ; Enable INT0 interupt to allow wakeup from Sleep command - Triggered by PWR_SW , active Low
OSCCON.7 =0 ' clear IDLEN bit ready for sleep command
@ sleep ; sleep command

return

[HenrikOlsson]

Hi Sheldon,

I'm not sure I can be of much assistance here but WPU are only available when the TRIS-bit is set. That is, when the pin is an output (TRIS-bit cleared) the WPU for that pin is disabled. So no, having the WPU enabled on an output pin, when in sleep mode or otherwise, is not normal and not something that should be happening.

However, when entering sleep mode, all the peripherals are turned off (no longer clocked) but outputs that are being driven will be kept 'on' during sleep so any load you have on those outputs will be reflected in the total current drawn by the PIC.

/Henrik.

[longpole001]

hi hendrick , yes i should have been more clear , the tris is set to input , with week pullups enabled , which shows the pin as high (output) during sleep mode

i did try shut those down prior to sleep , which helped but in the end i needed them on so i can use the power sw

think the cct is set for min of 3ma i try find where the leaks are

be good if someone knows the chip well for settings for low power , suck nothing at all sleep
i have good LDO which is powering the cpu at 3v3 with no load on the output and enabled i get about 0.3ma


i have a mosfet controling the 3v3 to anything external to the cpu

[HenrikOlsson]

Hi Sheldon,

Well, if you enable the internal pull-up resistor then "of course" the pin measures "high" - it's being pulled high by the resistor.

The pullup current, according to the datasheet, is 50-400uA @Vdd=5.5V so if you have the pullup resistor enabled and ground the pin you'll get a current of 45-360uA thru the Vdd pin, thru the WPU resistor, out thru the pin and to GND. If you do the same thing with two pins, then another 45-360uA and so on. (This is with Vdd @5V).

The current draw you meassure, is that of the PIC itself or on the input to the LDO? What's the quiescent current of the regulator?

/Henrik.

[longpole001]

i have made the pcb , so need to isolate every thing and work backward , but seems i am still looking at about 2ma , which i was hoping to get to about 0.7ma , 1ma max ,
i would like eventuly put the wdt on every 15 - 30 mins for rf update to the cct but i want to get as low as i can before considering that

[longpole001]

measured load value is at the output of the ldo of 2ma ,with only cpu , pullups enabled , power mostet Pch turned off to disable external load

with the output from ldo pcb track cut and ldo active so no no load i get 0.3ma at the input to the ldo , ldo had max drop of 250mv below 300ma

[longpole001]

ldo

http://www.farnell.com/datasheets/1756333.pdf

[Gusse]

Try to change all ports to inputs before entering sleep.
With 18F4520 I can see big difference if I don't do that (~2mA vs 200uA, incl. quiescent current of the regulator).
After sleep change ports back to normal settings before executing next steps.

Also disable pull-ups and use external pull-up with power sw.

[HenrikOlsson]

Hi,

Can you post the circuit diagram so we can see what's connected to what?

If you have an input with a pullup resistor (internal or external) and that input is pulled low by whatever is interfaced to it then current WILL flow thru pullup resistor and contribute to the total current drawn by the circuit.
Going to external pullup resistors powered thru a MOSFET won't gain much compared to simply disabling the internal pullups - as far as I can see.

The dropout voltage of the regulator doesn't have much to do with this. It's the "idle current" you're interested in, how much the regulator itself consumes in order to operate. The datasheet states 150uA max

/Henrik.

[LinkMTech]

My experience with the PIC18F14K50 and Sleep mode.

First thing I would suggest is to add @NOP right after the @ SLEEP command.
It could be the rascal is not even going to sleep!

Next make any unused pins an output (HIGH). Left floating as inputs was causing erratic higher Sleep currents that varied in the 10's to 100's of uA.

One last thing that really cleaned house before going to sleep was @RESET.
But my routine was structured to power up then go right to sleep until an IOC occurred that woke it up.
After chores were done and activity was quiet for a little and nothing happening.... @RESET... get back to sleep!

And of course the as the guys suggested, all external loads to the PIC need to be considered, they add up.

[longpole001]

ok will try those suggestions

as test for current
i just had the LDO regulator and smoothing caps only - current draw was 0.25ma
with CPU added on a bare board,
blank cpu , no other componets except a 4k7 resistor on the MCLR pin pulled high , current draw 2.8ma( note: tried a 100k resistor as pullup with same results)
when the cpu was held in reset state by pulling 4k7 to low - current draw was 1.5ma


its interesting that the cpu is at 2.8ma with no code in it

[longpole001]

UPDATE

well i founds some of the current leek during " sleep"
started out at 3ma
1. turning all the peripherals off - mainly the serial port which is connected to a usb module on the pcb , help reduce it by 0.9ma - brought it down to 2.1ma

2. making all ports inputs except where i need the 1 output to be high during the shut down reduced it by 0.3ma help in sleep mode - 1.8ma
3. only leaving on 1 pullups, i need during sleep also helped by 0.35ma -1.45ma


i am not convinced yet i have turned off the internal regulator, or got as low as i should be able to yet for ultra low power mode for sleep ,
i still believe i can get below 1ma

could someone review the config settings to see if i missed anything else
cheers

sheldon



' config for 18F46K80

#CONFIG

;----- CONFIG1L Options --------------------------------------------------
CONFIG XINST = OFF
CONFIG SOSCSEL = DIG ; Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled
CONFIG INTOSCSEL = LOW ; LF-INTOSC in low-power mode during Sleep
CONFIG RETEN = ON ; Ultra Low power regulator is Enabled (Controlled by SRETEN bit)when in sleep

;----- CONFIG1H Options --------------------------------------------------
CONFIG IESO = OFF
CONFIG FCMEN = OFF
CONFIG PLLCFG = ON
CONFIG FOSC = INTIO2 ; Internal RC oscillator , PORTA.6 , PORTA.7 as I/O

;----- CONFIG2L Options --------------------------------------------------
CONFIG BORPWR = ZPBORMV ; ZPBORMV instead of BORMV is selected
CONFIG BORV = 2 ; 2V
CONFIG BOREN = SBORDIS ; Enabled in hardware, SBOREN disabled
CONFIG PWRTEN = OFF

;----- CONFIG2H Options --------------------------------------------------
CONFIG WDTPS = 512 ; 1:512
CONFIG WDTEN = OFF ; WDT Off

;----- CONFIG3L Options --------------------------------------------------
; no register in the device

;----- CONFIG3H Options --------------------------------------------------
CONFIG MCLRE = ON ; MCLR ENabled FOR DIAG , RG5 DISabled
CONFIG MSSPMSK = MSK7 ; 7 Bit address masking mode
CONFIG CANMX = PORTB ; ECAN TX and RX pins are located on RB2 and RB3, respectively

;----- CONFIG4L Options --------------------------------------------------
CONFIG BBSIZ = BB1K ; 1K word Boot Block size
CONFIG STVREN = ON

;----- CONFIG5L Options --------------------------------------------------

CONFIG CP0 = ON ; MEMORY BLOCK 0 CODE PROTECT BIT - 7KW 800h - 3FFFh ( when 1K BOOT OPTION used )
CONFIG CP1 = ON ; MEMORY BLOCK 1 CODE PROTECT BIT - 8KW 4000h - 7FFFh
CONFIG CP2 = ON ; MEMORY BLOCK 2 CODE PROTECT BIT - 8KW 8000h - BFFFh
CONFIG CP3 = ON ; MEMORY BLOCK 3 CODE PROTECT BIT - 8KW C000h - FFFFh


;----- CONFIG5H Options --------------------------------------------------
CONFIG CPD = OFF ; EEPROM DATA PREOTECT BIT - EXTERNAL R/W
CONFIG CPB = ON ; BOOT BLOCK CODE PROTECT BIT

;----- CONFIG6L Options --------------------------------------------------
CONFIG WRT0 = OFF ; MEMORY BLOCK WRITE PROTECT BIT
CONFIG WRT1 = OFF
CONFIG WRT2 = OFF
CONFIG WRT3 = OFF


;----- CONFIG6H Options --------------------------------------------------
CONFIG WRTD = OFF ; EEPROM WRITE PROTECT BIT - INTERNAL AND EXTERNAL
CONFIG WRTB = ON ; BOOT BLOCK WRITE PROTECT
CONFIG WRTC = ON ; CONFIGURATION REGISTER WRITE PROTECT BIT

;----- CONFIG7L Options --------------------------------------------------
CONFIG EBTR0 = OFF ; MEMORY READ TABLE BLOCK PROTECT
CONFIG EBTR1 = OFF
CONFIG EBTR2 = OFF
CONFIG EBTR3 = OFF

;----- CONFIG7H Options --------------------------------------------------
CONFIG EBTRB = OFF ; TABLE READ PROTECT BOOT

#ENDCONFIG
clear ' clear all varables to 0 on startup











OSCCON = %01100000 ' Select 32Mhz - using 8Mhz internal with PPLx4 in Config1H<3:0> = IDLEN =0 , 8Mhz , OSTS=0,RFIOFS=1,RC_Run (1x) OSC using PLL
' Bit 7 IDLEN =0 ( sleep mode when sleep instraction executed)
' Bits 6-4 - 111 = 16Mhz , 110 = 8MHz ,101 = 4 MHz, 100 = 2MHz 011 = 1MHz
' If INTTSRC=0 and MFIOSEL= 0 then 010 = HF-INTOSC/32 (500Khz), 001 = HF-INTOSC/64 (250Khz) ,000 = LF-INTOSC (31.25Khz)
' If INTTSRC=0 and MFIOSEL= 1 then 010 = MF-INTOSC (500Khz), 001 = MF-INTOSC/2 (250Khz) ,000 = LF-INTOSC (31.25Khz)
' If INTTSRC=1 and MFIOSEL= 0 then 010 = HF-INTOSC/32 (500Khz), 001 = HF-INTOSC/64 (250Khz) ,000 = HF-INTOSC/512 (31.25Khz)
' If INTTSRC=1 and MFIOSEL= 1 then 010 = MF-INTOSC (500Khz), 001 = MF-INTOSC/2 (250Khz) ,000 = MF-INTOSC/16 (31.25Khz)
' Note: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>
' Bit 3 - OSTS = 0 - Osc startup time out is ruinning from internal OSC ( HF, MF or LF-INTOSC)
' Bit 2 - HFIOFS =1 ( INTOSC Frq stable bit - 1 = stable , 0 = not stable
' Bits 1-0 - 00= Dephalt Pri OSc ( OSC1/2 or HF-INTOSC with/without PLL set in FOSC,3:0> config1H <3.0>
' 01 = SOSC osc
' 1x = Internal osc ( LF, MF,HF-INTOSC)

' OSCCON2 = $00 ' Bit 7 n/a , Bit 6 - SOSCRUN - Run status bit , Bit 5-4 n/a,
' Bit 3 = SOASCGO - Osc Start control bit 1 = OSC running , 0 = OSC shut off if no requests for it
' Bit 2 n/a , Bit 1 - MFIOFS 1= MFINTOSC stable 0 = Not stable
' Bit 0 MFIOSEL - 1 = MF-INTOSC replaces HF-ISTOSC Freq for 500Khz,250Khz,31.25KHz) 0 = MF-INTOSC not used

OSCTUNE = %01000000 ' Bit 7 - INTSRC - internal LF Source Select 1 = 31.25 from 16Mhz Internal /512 HF-INTOSC ) 0 = Internal 31khz OSC
' Bit 6 - PLLEN - 1 PLL enabled , 0 = PLL disabled
' Bits 5-0 Frequancy callibaration 00000 = centre Frq

WDTCON = %00010000 ' use ultra low power mode when in sleep - disable regulator in sleep mode
' Bit7 = REGSLP- Regulator Voltage Sleep Enable - 1= Reg goes into low-power Mode when in sleep mode ,0 = Reg stay in normal mode
' Bit6= n/a , Bit5 = ULPLVL - Ultra lowpower Wakeup output sel 1= Vout on RA0 0= Vout on RA1 ( no effect if WDTEN in config is set )
' Bit4= SRETEN = Regulator Volt Sleep Disable bit - 1= goes into Ultra lOwpower mode in sleep ( CONFIG1L.0 =0 MUST BE SET)
' Bit3=n/a , Bit2 = ULPEN - Ultra Low Power Wakup Module enable 1 = enabled , 0 = disabled
' Bit1=ULPSINK- Ultra Low-power Wakeup Current Sink Enable 1= Sink enabled 0 = Sink disabled ( Not valid if ULPEN=0 )
' Bit0= SWDTEN -Watchdog Timer Enable = 1= enable watchdog 0 = Disable Watchdog ( no effect if WDTEN in config is set )


PSPCON.4 = 0 ' turn off parallel slave port mode - general purpose I/O mode PORTD & PORTE



INTCON2.6 = 0 ' INTEDG0 - External Interrupt 0 Edge Select - 1= Rising Edge , 0 = Falling Edge
INTCON2.5 = 0 ' INTEDG1 - External Interrupt 1 Edge Select - 1= Rising Edge , 0 = Falling Edge
INTCON2.4 = 0 ' INTEDG2 - External Interrupt 2 Edge Select - 1= Rising Edge , 0 = Falling Edge
INTCON2.3 = 0 ' INTEDG3 - External Interrupt 3 Edge Select - 1= Rising Edge , 0 = Falling Edge

INTCON3.6 = 0 ' INT1IP - INT1 External Interupt Priority - 1 = High Priorty , 0 = Low Priority
INTCON3.7 = 0 ' INT2IP - INT2 External Interupt Priority - 1 = High Priorty , 0 = Low Priority
INTCON2.1 = 0 ' INT3IP - INT3 External Interupt Priority - 1 = High Priorty , 0 = Low Priority







' =========== Power Shutdown routine ==================
Shut_Down:

pwr_on = 1 ' PWR ON = 1 = OFF - turns off power to devices external to cpu
@ INT_DISABLE RBC_INT ; TURN OFF PortB IOC Interrupts for RX_mode - RF_IRQ pin
@ INT_DISABLE RX2_INT ; Turn Off USART RX Interrupts for RX_mode - RX input on USART
@ INT_DISABLE TMR0_INT ; disable Timer0 interupts

TRISA = $FF ' reduce power usage by puting port to inputs
TRISC = $FF
TRISD = $F7 ' make all ports inputs except portd.3 for PWR_ON output
TRISE = $FF

WPUB = $01 ' Port B set to inputs already , turn off all week pullups except Pwr_sw input

PMD0 = $FF ' TURN OFF ALL PERIPHERALS ON CPU
PMD1 = $FF
PMD2 = $FF

PWR_shutdown = 0 ' CLEAR shutdown flag
INTCON.1 = 0 ' CLEAR INT0 interupt flag prior to enable
@ INT_ENABLE INT0_INT ; Enable INT0 interupt to allow wakeup from Sleep command - Triggered by PWR_SW , active Low
OSCCON.7 =0 ' clear IDLEN bit ready for sleep command
@ sleep ; sleep command
@ NOP

return

' ----------------------------------------------------------

Sleep_Over:
' Interupt routine to recover from the sleep command

@ reset ; just reset device
@ INT_RETURN
return