PBP command execution time

[Demon]

Main logic snippet:

...
mainloop:
TRISA = %11111100
PORTA = %00000001

PORTA = %00000010
goto mainloop
End


ASM listing:

...
LABEL?L _mainloop
MOVE?CB 0FCh, TRISA
MOVE?CB 001h, PORTA
MOVE?CB 002h, PORTA
GOTO?L _mainloop
END?

END

Saleae sampling:
7524

1 uSec per instruction at 8MHz on a 18F44K22.

Is it that simple? Or is there more going on and I'm not getting it?

(1978-1984 is so far away. Yeah, I didn't have sec 5 math so I had to take it before starting 3-yr data processing program. Of course I dropped out sec 5 math on first try; culture shock coming from high school where teachers kicked me in the butt to get things done :D and had to come back the next September to get it done.)

Robert

[richard]

@8mhz each instruction takes 0.5uS what you are looking at there are macro's you need the asm to see the actual code


it wood go something like

mainloop:
movf 0fh,w
movwf trisa
movf 1,w
movwf porta
movf 0,w
movwf porta
goto mainloop

ps pbp probably sticks a clrwdt in there somewhere too

[Demon]

I found this by looking for mainloop in the LST file:


...
00086 LABEL?L _mainloop
M RST?RP
M if (PREV_ALT != 0)
M bcf WDTCON, ADSHR
M PREV_ALT = 0
M endif
M if (PREV_BANK != 0)
M movlb 0
M PREV_BANK = 0
M endif
M ifdef PM_USED
M LALL
M _mainloop
M XALL
M else
000074 M _mainloop
M endif
00087 MOVE?CB 0FCh, TRISA
M CHK?RP TRISA
M if (((TRISA) & 8000h) != PREV_ALT)
M if ((TRISA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (TRISA) & 8000h
M endif
M if ((((TRISA) & 0fffh) > BANKA_END) & (((TRISA) & 0fffh) < (0f01h + BANKA_END)))
M if (((TRISA) & 0f00h) != (PREV_BANK << 8))
M movlb high (TRISA)
M PREV_BANK = high (TRISA)
M endif
M endif
M if (low (0FCh) == 0)
M clrf TRISA
M else
M if (low (0FCh) == 255)
M setf TRISA
M else
000074 0EFC M movlw low (0FCh)
000076 6E92 M movwf TRISA
M endif
M endif
MPASM 5.49 BLINK1~1.ASM 12-15-2014 22:49:14 PAGE 15


LOC OBJECT CODE LINE SOURCE TEXT
VALUE

00088 MOVE?CB 001h, PORTA
M CHK?RP PORTA
M if (((PORTA) & 8000h) != PREV_ALT)
M if ((PORTA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (PORTA) & 8000h
M endif
M if ((((PORTA) & 0fffh) > BANKA_END) & (((PORTA) & 0fffh) < (0f01h + BANKA_END)))
M if (((PORTA) & 0f00h) != (PREV_BANK << 8))
M movlb high (PORTA)
M PREV_BANK = high (PORTA)
M endif
M endif
M if (low (001h) == 0)
M clrf PORTA
M else
M if (low (001h) == 255)
M setf PORTA
M else
000078 0E01 M movlw low (001h)
00007A 6E80 M movwf PORTA
M endif
M endif
00089 MOVE?CB 002h, PORTA
M CHK?RP PORTA
M if (((PORTA) & 8000h) != PREV_ALT)
M if ((PORTA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (PORTA) & 8000h
M endif
M if ((((PORTA) & 0fffh) > BANKA_END) & (((PORTA) & 0fffh) < (0f01h + BANKA_END)))
M if (((PORTA) & 0f00h) != (PREV_BANK << 8))
M movlb high (PORTA)
M PREV_BANK = high (PORTA)
M endif
M endif
M if (low (002h) == 0)
M clrf PORTA
M else
M if (low (002h) == 255)
M setf PORTA
M else
00007C 0E02 M movlw low (002h)
00007E 6E80 M movwf PORTA
M endif
M endif
00090 MOVE?CB 0F3h, TRISA
MPASM 5.49 BLINK1~1.ASM 12-15-2014 22:49:14 PAGE 16


LOC OBJECT CODE LINE SOURCE TEXT
VALUE

M CHK?RP TRISA
M if (((TRISA) & 8000h) != PREV_ALT)
M if ((TRISA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (TRISA) & 8000h
M endif
M if ((((TRISA) & 0fffh) > BANKA_END) & (((TRISA) & 0fffh) < (0f01h + BANKA_END)))
M if (((TRISA) & 0f00h) != (PREV_BANK << 8))
M movlb high (TRISA)
M PREV_BANK = high (TRISA)
M endif
M endif
M if (low (0F3h) == 0)
M clrf TRISA
M else
M if (low (0F3h) == 255)
M setf TRISA
M else
000080 0EF3 M movlw low (0F3h)
000082 6E92 M movwf TRISA
M endif
M endif
00091 MOVE?CB 004h, PORTA
M CHK?RP PORTA
M if (((PORTA) & 8000h) != PREV_ALT)
M if ((PORTA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (PORTA) & 8000h
M endif
M if ((((PORTA) & 0fffh) > BANKA_END) & (((PORTA) & 0fffh) < (0f01h + BANKA_END)))
M if (((PORTA) & 0f00h) != (PREV_BANK << 8))
M movlb high (PORTA)
M PREV_BANK = high (PORTA)
M endif
M endif
M if (low (004h) == 0)
M clrf PORTA
M else
M if (low (004h) == 255)
M setf PORTA
M else
000084 0E04 M movlw low (004h)
000086 6E80 M movwf PORTA
M endif
M endif
00092 MOVE?CB 008h, PORTA
M CHK?RP PORTA
MPASM 5.49 BLINK1~1.ASM 12-15-2014 22:49:14 PAGE 17


LOC OBJECT CODE LINE SOURCE TEXT
VALUE

M if (((PORTA) & 8000h) != PREV_ALT)
M if ((PORTA) & 8000h)
M bsf WDTCON, ADSHR
M else
M bcf WDTCON, ADSHR
M endif
M PREV_ALT = (PORTA) & 8000h
M endif
M if ((((PORTA) & 0fffh) > BANKA_END) & (((PORTA) & 0fffh) < (0f01h + BANKA_END)))
M if (((PORTA) & 0f00h) != (PREV_BANK << 8))
M movlb high (PORTA)
M PREV_BANK = high (PORTA)
M endif
M endif
M if (low (008h) == 0)
M clrf PORTA
M else
M if (low (008h) == 255)
M setf PORTA
M else
000088 0E08 M movlw low (008h)
00008A 6E80 M movwf PORTA
M endif
M endif
00093 GOTO?L _mainloop
M L?GOTO _mainloop
...

A lot more going on before and after that snippet.

Robert

[Demon]

@8mhz each instruction takes 0.5uS ...

How do we get calculate 0.5uS again? I never remember how to do that. I'm sure the datasheet comes into play.



...ps pbp probably sticks a clrwdt in there somewhere too

Yup, right after the GOTO at the bottom.

Robert

[richard]

that why your own asm routines are often used , if you know every thing is in the same mem bank then ALL that bank ckecking (chk:rp) can be eliminated ,but what you have there is a lst file I would expect any decent compiler to optimise most if not all that unnecessary code out , the assembled file should look cleaner than that, but need to disassemble the hex file to see it

[Demon]

When I look in the folder where I compile, I see that ASM file I copied above, plus BAS, HEX, LST, MAC and O files.

I don't see a "trimmed" assembler file.

Robert

[richard]

How do we get calculate 0.5uS again? I never remember how to do that. I'm sure the datasheet comes into play.

each instruction takes 4 clock cycles . a clock cycle is 1/8000000 = 125nS therefore 1 instruction = 4*125 nS = 0.5uS

[richard]

When I look in the folder where I compile, I see that ASM file I copied above, plus BAS, HEX, LST, MAC and O files.

my bad
I really meant the actual assembled code ---- you need a disassembler to see what really happened

[Demon]

each instruction takes 4 clock cycles . a clock cycle is 1/8000000 = 125nS therefore 1 instruction = 4*125 nS = 0.5uS

Unless I can't use a Saleae probe properly, each asm macro ran in 1uS (4uS for one pass). That's not bad considering the chunk of asm in there.

Robert

[Demon]

... you need a disassembler to see what really happened

So Darryl must have been using a development tool to know exactly what was going on in the background?

Robert

[richard]

each asm macro ran in 1uS (4uS for one pass). That's not bad considering the chunk of asm in there.
means the compiler is making nicely optimised code
I'm sure dt would have had some nice tools , my disassembler won't function any longer it steeps back to windows98 days , but since I gave up hand assembly its not missed that much .
imho most compliers do a reasonable job except maybe the free version of xc8 which is apparently deliberately de-optimised

[HenrikOlsson]

Unless I can't use a Saleae probe properly, each asm macro ran in 1uS (4uS for one pass). That's not bad considering the chunk of asm in there.
I think you're not using it properly. As far as I can see you have the sampling rate set to 4Mhz, so there's no way the logic analyzer is going to resolve anythning shorter than 1us. Increase the sampling rate and see if it makes any difference.

By the way, these chk:rp macro things, aren't those assembler macros, ie they check, at compile time, if there's a need to switch banks and only then actually inserts the code? Ie, chk:rp isn't runtime code, it's assembly time code.

/Henrik.

[Demon]

I can't, I tried 8MHz but the software said it couldn't keep up and lowered the speed.


EDIT: So I tried another approach and lowered the OSC speed, but I get INVALID OSC DEFINE whenever I try DEFINE OSC 1 or 2.

PIC 18F44K22, PBP 2.60c, MPASM v5.49


asm
; __CONFIG _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_ON_1H & _PRICLKEN_OFF_1H & _FCMEN_ON_1H & _IESO_OFF_1H
__CONFIG _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_OFF_1H & _PRICLKEN_OFF_1H & _FCMEN_ON_1H & _IESO_OFF_1H
__CONFIG _CONFIG2L, _PWRTEN_ON_2L & _BOREN_SBORDIS_2L & _BORV_285_2L
__CONFIG _CONFIG2H, _WDTEN_OFF_2H
__CONFIG _CONFIG3H, _CCP2MX_PORTC1_3H & _PBADEN_OFF_3H & _CCP3MX_PORTE0_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _P2BMX_PORTC0_3H & _MCLRE_EXTMCLR_3H
__CONFIG _CONFIG4L, _STVREN_OFF_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
endasm

DEFINE OSC 1
;DEFINE OSC 64

OSCCON = %00110000 ' OSCILLATOR CONTROL REGISTER
;OSCCON = %01110000 ' OSCILLATOR CONTROL REGISTER
' bit 7 IDLEN: Idle Enable bit
' R/W 1 = Device enters Idle mode on SLEEP instruction
' 0 = Device enters Sleep mode on SLEEP instruction
' bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits(2)
' R/W 111 = HFINTOSC – (16 MHz)
' 110 = HFINTOSC/2 – (8 MHz)
' 101 = HFINTOSC/4 – (4 MHz)
' 100 = HFINTOSC/8 – (2 MHz)
' 011 = HFINTOSC/16 – (1 MHz)(3)
' If INTSRC = 0 and MFIOSEL = 0:
' 010 = HFINTOSC/32 – (500 kHz)
' 001 = HFINTOSC/64 – (250 kHz)
' 000 = LFINTOSC – (31.25 kHz)
' If INTSRC = 1 and MFIOSEL = 0:
' 010 = HFINTOSC/32 – (500 kHz)
' 001 = HFINTOSC/64 – (250 kHz)
' 000 = HFINTOSC/512 – (31.25 kHz)
' If INTSRC = 0 and MFIOSEL = 1:
' 010 = MFINTOSC – (500 kHz)
' 001 = MFINTOSC/2 – (250 kHz)
' 000 = LFINTOSC – (31.25 kHz)
' If INTSRC = 1 and MFIOSEL = 1:
' 010 = MFINTOSC – (500 kHz)
' 001 = MFINTOSC/2 – (250 kHz)
' 000 = MFINTOSC/16 – (31.25 kHz)
' bit 3 OSTS: Oscillator Start-up Time-out Status bit
' R 1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register
' 0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC)
' bit 2 HFIOFS: HFINTOSC Frequency Stable bit
' R 1 = HFINTOSC frequency is stable
' 0 = HFINTOSC frequency is not stable
' bit 1-0 SCS<1:0>: System Clock Select bit
' R/W 1x = Internal oscillator block
' 01 = Secondary (SOSC) oscillator
' 00 = Primary clock (determined by FOSC<3:0> in CONFIG1H).

OSCCON2 = %00000100 ' OSCILLATOR CONTROL REGISTER 2
' bit 7 PLLRDY: PLL Run Status bit
' R 1 = System clock comes from 4xPLL
' 0 = System clock comes from an oscillator, other than 4xPLL
' bit 6 SOSCRUN: SOSC Run Status bit
' R 1 = System clock comes from secondary SOSC
' 0 = System clock comes from an oscillator, other than SOSC
' bit 5 Unimplemented: Read as ‘0’.
' bit 4 MFIOSEL: MFINTOSC Select bit
' R/W=0 1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
' 0 = MFINTOSC is not used
' bit 3 SOSCGO(1): Secondary Oscillator Start Control bit
' R/W=0 1 = Secondary oscillator is enabled.
' 0 = Secondary oscillator is shut off if no other sources are requesting it.
' bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit
' R/W=1 1 = Oscillator drive circuit on
' 0 = Oscillator drive circuit off (zero power)
' bit 1 MFIOFS: MFINTOSC Frequency Stable bit
' R 1 = MFINTOSC is stable
' 0 = MFINTOSC is not stable
' bit 0 LFIOFS: LFINTOSC Frequency Stable bit
' R 1 = LFINTOSC is stable
' 0 = LFINTOSC is not stable

OSCTUNE = %10000000 ' OSCILLATOR TUNING REGISTER
;OSCTUNE = %11000000 ' OSCILLATOR TUNING REGISTER
' bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
' R/W 1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source
' 0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator
' bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1)
' R/W 1 = PLL enabled
' 0 = PLL disabled
' bit 5-0 TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies
' R/W 011111 = Maximum frequency
' 011110 =
' • • •
' 000001 =
' 000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated frequency.
' 111111 =
' • • •
' 100000 = Minimum frequency

[HenrikOlsson]

Robert,
1, 2 MHz aren't supported oscillator speeds. From the manual:

There are a limited number of valid numbers that can be used: 3 (3.58MHz), 4, 8, 10, 12, 16, 20, 24, 25, 32, 33, 40, 48, 64. These are the only frequencies for which PBP is able to accurately calibrate its timing.

As for the Saleae LOGIC....Your computer can't keep up due to loading on the USB bus (or too much other stuff going on). Make sure that the LOGIC it's the only device on that USB Host controller. If you don't know, just try another USB port.

But, I don't know what was wrong with me this morning. I was probably thinking in terms of instruction cycles of the PIC.....
If the samplig rate is 4MHz then the shortest resolvable time is of course 250ns and not 1us as I wrote. Even so I'd definitely try to get the sample rate up a notch (or two).

/Henrik.

[Demon]

I was fixated looking at the INCLUDE file, not the manual.

And I realized after I went to bed that I am offset by one command in my Saleae pic in the other thread. The action occurs AFTER the command, not before, d'uh.

I remove all other USB peripherals when I do my test and was able to run the pgm at 4MHz and the probe at 8MHz.

I still get the same structure, but with new timings naturally. It doesn't seem the be missing anything, and it seems neither was the previous attempt.
7528


mainloop:
TRISA = %11111100
PORTA = %00000001 ' LED 1
PORTA = %00000010 ' LED 2

TRISA = %11110011
PORTA = %00000100 ' LED 3
PORTA = %00001000 ' LED 4
goto mainloop
End


Robert

[HenrikOlsson]

Hi,
As Richard pointed out earlier, something like TRISA = %11111100 or PortA = %00000001 compiles to TWO assembly instructions:
movlw low (0FCh)
movwf TRISA
each taking one instruction cycle. If the PIC is clocked at 4MHz, one instruction cycle is 1us so TRISA = %11111100 takes two us.

The Goto MainLoop compiles to a bra instruction which takes two instructions.

Your complete program executes in 14 cycles, or 14us at 4MHz.

Then, as have also been pointed out, the compiler MAY inject a clear WDT instruction. Turn it off and tell the compiler to stop tickle the dog if you want to be sure.

/Henrik.

[Demon]

Yup, I got those values also by highlighting from one point in a pass to the same point in the next pass. I couldn't point before the top TRIS, there's no pulse break to select. That's why I used after PORT instead, I can select it at the beginning and end of a pass.
7529