Having Serin Serout problems

[Elusiveinc]

I'm trying to make several modules that configure themselves automatically as master and slaves all pics being programed with the exact same code. I'm using serin with a timeout and serout. I only have 4 modules built. and it recognizes properly about 70% of the time with 4. I need it to recognize properly every time up to 16 modules. Also I am sending serout 4 times more that I would like. After master is set it sits and waits for ground pluses from each slave so the master knows how many slaves there are. I am sending serin and out on same wire as I am sending the ground pulses back to the master but the ground pulse back happens after serout is complete. Any help would be greatly appreciated. Also just a question how does PBP know on serin when you use a time out that it just isn't more bytes to be sent.(head scratcher since documentation in PBP3 book is kind of vague. just commas) also using onboard oscillators, and B.0 for serin commands and B.1 for serout commands. and the problem I seem to be having when it doesn't sync properly is that serin times out. because down the communication line the 2nd or 3rd module with say its the master also with slaves.
here is my code.

Initial: if ign=1 then
goto initial
else
Initiall: if x=0 then
serin ign, 2, 600, setmaster, ["~"], module
goto setmaster
else
pause 50
seroutrpt: if a<=5 then 'sends serout command 5 times
serout OUT, 2,["~",module]
a=a+1
goto seroutrpt
endif
trisb.1=1 'makes out and input temporarly
trisb.0=0 'makes ign and output temporarly
ign=0 'sends ground pulse to previous slave for slave count
pause 50
ign=1 'idles pulse
goto waitcnt
endif
endif
setmaster: Write 1, module
OUT=0 'wakes next slave to get ready for serin
pause 50
out=1 'gets exsisting ready for serout
x=1 'been through one cycle for serin now will serout
module=module+1
goto Initiall
waitcnt: read 1, master1
if master1=0 then
temp=0
count out, 4000, temp 'counts how many pulses on masters out pin in 4 sec
write 5, temp 'writes how many slaves in series
trisb.0=1 'sets ign back to input
trisb.1=0 'sets out back to output
goto begin
else
keeploop: ign=1 'counts loop for when passthrough is not active
if temp < 255 then 'sets delay loop to keep checking for inputs
if out=0 then
while out=0
ign=0
wend
goto keeploop
else
temp=temp+1
pause 15
goto keeploop
endif
else
trisb.0= 1 'resets b.0 to input
trisb.1= 0 'resets b.1 to output
temp=0
goto begin
endif
endif

thank you,
Joe

[Demon]

Have you tried with just master and 1 slave? Make sure slaves aren't talking at the same time first, then add 1 slave at a time.

A schematic how you wire the PICs would help.

Robert

[mackrackit]

Just a quick read through...
You do not reset "a" to zero after this routine, think what will happen the next time this routine is called, when a=6.


seroutrpt: if a<=5 then 'sends serout command 5 times
serout OUT, 2,["~",module]
a=a+1
goto seroutrpt
endif

[Elusiveinc]

6957

Demon: with just a slave and a master. It still only works most of the time not all. Thinking about adding a pull up resister to connecting lines. Kind of been wondering if the internal pull ups are not enough to keep logic high while the serin processor is waiting for serout processor.

mackracket: The "a" gets reset later in the program. Each micro only makes the loop one time. a cycle of serin and serout. If my logic is correct it won't matter in this section.


This is my first time playing with serin and serout. at 9600 baud on a 8mhz chip. Should be extremely reliable right?

[Demon]

First time through that logic, what guarantees the initial values of X and A?

9600baud at 8MHz has 0.16% error rate for hardware USART, I assume it should be somewhat similar for software communication.

Internal pull-ups should be adequate. Personallly I'd put a pull-up on all B0 pins; I don't trust myself to configure internal pull-ups properly.

Robert

[Demon]

This is confusing.



Initial:
if ign=1 then
goto initial
else
Initiall:
if x=0 then
serin ign, 2, 600, setmaster, ["~"], module
goto setmaster
else
pause 50
seroutrpt:
if a<=5 then 'sends serout command 5 times
serout OUT, 2,["~",module]
a=a+1
goto seroutrpt
endif
trisb.1=1 'makes out and input temporarly
trisb.0=0 'makes ign and output temporarly
ign=0 'sends ground pulse to previous slave for slave count
pause 50
ign=1 'idles pulse
goto waitcnt
endif
endif



You can do simple IF for first test:



Initial:
if ign=1 then
goto initial
endif

Initiall:
if x=0 then
serin ign, 2, 600, setmaster, ["~"], module
goto setmaster
else
pause 50
seroutrpt:
if a<=5 then 'sends serout command 5 times
serout OUT, 2,["~",module]
a=a+1
goto seroutrpt
endif
trisb.1=1 'makes out and input temporarly
trisb.0=0 'makes ign and output temporarly
ign=0 'sends ground pulse to previous slave for slave count
pause 50
ign=1 'idles pulse
goto waitcnt
endif



There are other ways to make constant loops too (WHILE-WEND for example).

It would definitely help if you posted all your code.

(I'm still digesting the rest of the logic, bit confusing for me)

Robert

[Demon]

While you're changing pins from inputs to outputs lower in the chain, how does the PIC higher in the chain know to change as well?

Robert

EDIT: This is what we used to call daisy-chain design, there's a reason why it's not used much any more. :)

There's a reason why people use 2 programs; one dedicated to program a master and another for the slaves. I'm sure you can get this working, somehow, but it's so much simpler to use newer designs.

Too bad you're using 16F818, it doesn't have hardware USART. You could do this at 115200baud, the master runs at 48MHz, the slaves at 64MHz:
http://www.picbasic.co.uk/forum/showthread.php?t=17282

[Elusiveinc]

I'm trying to make it idiot proof(trying to prevent 10k phone calls because people are to lazy to read instruction sheet) and I only want to sell one sku if at all possible. and I could make another data line. But I would like only three wires between modules vcc, ground, and data.

a and x are initialized to 0 two lines above don't know why I didn't include that. And you are correct on the if statement.

The way that it works:

All processors Idle till they receive a 0 on ign. Once the first processor in line goes to zero. It goes to serin. if serin times out. This processor is then assumed to be the master. module is incremented by one to send ID to next processor. It then sends a ground signal out of "out" to advanced the next processor into serin. The master then serouts 5 times (even though I want it to be one). Then goes to a pulse counting state on "out". The second processor receives its module number from serin. stores to eeprom then, increments "module" sends a ground pulse to next processor to get it ready for serin in. After that each slave after that does the same. after it sends serout to next processor. It sends a ground pulse back to previous processor to count. Then it listens on "out" for ground pulse and everytime it gets a ground pulse it just sends the pulse out of "ign" back to the master which then counts how many slaves have been generated. Everything in program works flawlessly except for the serin and serout. as for some reason serin times out and then a slave thinks it is the master also. Just need to know why this is. It is either setup timing, noise (doubt it) or possibly when in serin state it looses its pull up resistor state on B.0 (which is enabled)

[Demon]

... I would like only three wires between modules vcc, ground, and data.
...

You might have a point with the internal pull-up resistor being disrupted with the pin being used as input and output. Try an external on each B0, see how that goes.

Robert