confusion with the CD74HC165 8 bit register

[lerameur]

Hi,

I am just trying to use the CD74HC165 chip to see the serial 8 bit output, but its giving me nothing. I do not understand the PL, CP and CE ports, and there no explanation in the datasheet, can some explain to me these three ports??

thanks

K

[HenrikOlsson]

Hi,
The '165 is an 8bit parallel in/serial out shift register. If reading it with PBP you use the Shiftin command. I mention this because you say you're trying see the 8bit serial output which to me sounds as if your trying to use with Shiftout. The DS input of the chip is a serial input but there's no way to "see" the data being shifted in, it's used to shift data "thru" the device when cascading several '165's.

OK, the PL input is what "loads" the 8 bits of data (D0-D7) into the internal shift register. CP and CE are the two clock inputs, CP is active high, CE is active low.

This datasheet (http://www.nxp.com/documents/data_sheet/74HC_HCT165.pdf) has a pretty good description of how it works.

/Henrik.

[lerameur]

I was trying to use serin command. Cause the chip is parallel in - serial out. Do I need to sent a special signal for CP, or PBP takes care of that ?

[HenrikOlsson]

Serin is for asynchronous serial communication and can't be used with that shiftregister. You need to use Shiftin which is for synchronous serial communication.

With the Shiftin command you specify two pins, one for the data and one for the clock. First you need to load/latch the data into the shiftregister by pulsing the PL pin, then the Shiftin command is used to shift data out of the '165 and into the PIC.

[lerameur]

I understang you are mentionning two pins, one clocking and one input. Although the datasheet mentions PL and CP for input, Then Q7 for serial output. That would mean three pins, so we dont need CE pin ??.

K

[lerameur]

I think I have things cleared up. Data is Q7, Clock=CP, Pulse=PL (send a signal to receive the byte with shiftin command) and CE is grounded. ?!?

[HenrikOlsson]

Hi,
Yes, PL is parallel load - a logic low level on this input is what loads the shiftregister with the 8 databits. This way you know that all bits you shift in is from the "same moment in time". The Shiftin command does not handle this pin for you, you need to pulse it "manualy".

Correct, Q7 is the serial output of the shiftregister.

CE is chip enable or clock enable if you like, pull it low to use the CP pin as a positive clock input or tie the CP high and use the CE pin as a negative clock input.

Note that the '165 does not "send" the data out when you pulse the PL pin. It is the Shiftin command that "pulls" the data out of the shiftregsiter. Shiftin generates the clock pulses the '165 uses to shift the databits thru the shiftregister.

[falingtrea]

Also the PL (parallel load) signal needs to be High in order to clock data out of the serial data pin, but also needs to go low in order to sample the data on the parallel pins. Simplest thing to do is to invert the CE signal and use that to control the PL signal. That is how I turned the HC165 into a simple SPI-like interface (Clock, Data out, and Chip Enable).

[lerameur]

Ok, I understand pretty much how the chip works, it was the bridge between how Picbasic language treat the shiftin code that was troubling me.

Ok I have this code on a Pic16F887, I am only getting '00' as my output, I tried switcing ports ( CP and PL just to see, but no luck). My parallel input have random 0 and 5v for try out.


'@ __config _CONFIG1, _INTRC_OSC_NOCLKOUT & _WDT_ON & _MCLRE_OFF & _LVP_OFF & _CP_OFF
OSCCON = %01110000 '8 Mhz
DEFINE OSC 8
ANSELH = 0


'/////////////////////////
'// LCD configuration //
'/////////////////////////

DEFINE LCD_DREG PORTB ' Set LCD Data port
DEFINE LCD_DBIT 4 ' Set starting Data bit (0 or 4) if 4-bit bus RB.4, RB.5, RB.6, RB.7
DEFINE LCD_RSREG PORTB ' Set LCD Register Select port
DEFINE LCD_RSBIT 1 ' Set LCD Register Select bit
DEFINE LCD_EREG PORTB ' Set LCD Enable port
DEFINE LCD_EBIT 0 ' Set LCD Enable bit
DEFINE LCD_BITS 4 ' Set LCD bus size (4 or 8 bits) '4 therefore put wire at 4, 5, 6 and 7 of LCD
DEFINE LCD_LINES 2 ' Set number of lines on LCD
DEFINE LCD_COMMANDUS 2500
DEFINE LCD_DATAUS 250
DEFINE CHAR_PACING 2000
pause 500



TRISE = %11111100 ' Set PORTE to all input

Clock var PORTE.0 'CP
Load var PORTE.1 'PL
Data_1 var PORTE.2 'Q7 out
input1 var byte

Mainloop:

pulsout Load,1
shiftin Data_1,Clock,0,[input1 \8]
lcdout $FE,1, "Shift in"
lcdout $FE,$C0, dec2 input1
pause 300



GOTO Mainloop
End

[mackrackit]

It has been a couple of versions of PBP since I have used a shiftin register, but I remember
something about the MODE numbers not working. I know, it should not make a difference.
Just for giggles try.

include "modedefs.bas"
'
'
'
shiftin Data_1,Clock,MSBPre,.....

[HenrikOlsson]

Hi,
Like Tim said, the PL needs to idle high in order to shift the data out. To load the 8 bits into the register you pulse it low - you're currently doing it the other way around. Set the Load pin high initially, the Pulsout will then produce a pulse with the correct polarity.

[lerameur]

Tim,
How do you invert the CE signal with the PL pin. Do you direct connect both pins with an inverter? I guess my hardwireing is wrong...

K

[lerameur]

putting the PL low .. something like that ??

TRISE = %11111100 ' Set PORTE to all input

Clock var PORTE.0 'CP
Load var PORTE.1 'PL
Data_1 var PORTE.2 'Q7 out
input1 var byte

Mainloop:

low Load
pulsout Load,10
shiftin Data_1,Clock,0,[input1 \8]
lcdout $FE,1, "Shift in"
lcdout $FE,$C0, dec2 input1
pause 300



GOTO Mainloop
End

[HenrikOlsson]

No, the other way around...it must idle HIGH. It should always be HIGH except for that moment you want to "capture" the 8 databits. Put a HIGH Load before your mainloop, the Pulsout command will then pulse it low for you.

[falingtrea]

Tim,
How do you invert the CE signal with the PL pin. Do you direct connect both pins with an inverter? I guess my hardwireing is wrong...

K

That is how I did it. Mode 0 looks like the proper one to select.

But, because of the way the PL signal works (CLK disabled if PL is low), you could wire the CE low and just use the PL signal to control operation. Just set PL high before you execute the SHIFTIN command and set it low after the command is finished.

[falingtrea]

putting the PL low .. something like that ??


I would do this (and make sure the CE pin is pulled low always) :

TRISE = %11111100 ' Set PORTE to all input

Clock var PORTE.0 'CP
Load var PORTE.1 'PL
Data_1 var PORTE.2 'Q7 out
input1 var byte

low Load

Mainloop:

high Load
shiftin Data_1,Clock,0,[input1 \8]
low Load

lcdout $FE,1, "Shift in"
lcdout $FE,$C0, dec2 input1
pause 300

GOTO Mainloop
End

[lerameur]

Hi I just tried your program modification and it do not work. Also some people say here it should be high and you say it should always be low, this is confusing.


'/////////////////////////
'// test program
'// Using the PIC16F887
'/////////////////////////

'/////////////////////////
'// Define section //
'/////////////////////////
include "modedefs.bas"

OSCCON = %01110000 '8 Mhz
DEFINE OSC 8
ANSELH = 0


'/////////////////////////
'// LCD configuration //
'/////////////////////////

DEFINE LCD_DREG PORTB ' Set LCD Data port
DEFINE LCD_DBIT 4 ' Set starting Data bit (0 or 4) if 4-bit bus RB.4, RB.5, RB.6, RB.7
DEFINE LCD_RSREG PORTB ' Set LCD Register Select port
DEFINE LCD_RSBIT 1 ' Set LCD Register Select bit
DEFINE LCD_EREG PORTB ' Set LCD Enable port
DEFINE LCD_EBIT 0 ' Set LCD Enable bit
DEFINE LCD_BITS 4 ' Set LCD bus size (4 or 8 bits) '4 therefore put wire at 4, 5, 6 and 7 of LCD
DEFINE LCD_LINES 2 ' Set number of lines on LCD
DEFINE LCD_COMMANDUS 2500
DEFINE LCD_DATAUS 250
DEFINE CHAR_PACING 2000
pause 500


TRISE = %11111100 ' Set PORTE to all input

Clock var PORTE.0 'CP
Load var PORTE.1 'PL
Data_1 var PORTE.2 'Q7 out
input1 var byte

low Load

Mainloop:

high Load
shiftin Data_1,Clock,0,[input1 \8]
low Load

lcdout $FE,1, "Shift in"
lcdout $FE,$C0, dec2 input1
pause 300

GOTO Mainloop
End

[lerameur]

Hum, I tried pretty much every combination with High, Low PL, Pauses, whatever I could think about. Change HC165, maybe it could be defect. Nothing, still showing Zero as my output.

K

[mackrackit]

Can you post a schematic?

[lerameur]

Hi Dave, I can do that, maybe tomorrow, Its only using three ports in my Pic16F887, how hard can it be. I tried to switch to PORTD:
Clock var PORTD.0 'CP
Load var PORTD.1 'PL
Data_1 var PORTD.2 'Q7 out
But no luck either Maybe the CD4014BE will be easier ??

ken

[mackrackit]

How is the shift register connected? Inputs pulled high/low, power,etc.

[lerameur]

well pin 16 is on 5V
pin 1 in D1
Pin 2 in D0
pin 9 is the data
8 in ground CE is ground, and the other 8 input pin some I have on 5v and some on ground .

K

[mackrackit]

Try pin 7 for the data line to the pic.

[mackrackit]

And go back to toggle-ing the load line.

[lerameur]

I will do it tonight, I think this is the inverted output

[falingtrea]

Simple explaination based on truth table:

While PL is low, anything that happens on the CP, CE and DS pins is ignored, levels on pins D0-D6 are saved into the internal shift registers, and D7 is saved into the shift register and output on Q7. So PL has to be low at some point in order to load the levels from the D0-D7 pins into the registers

When PL transitions from low to high, the last levels on D0-D7 are latched into the shift registers.

While PL is high, The CP, CE and DS pins start working and anything that happens on the D0-D7 pins is ignored. As long as the CE pin is low, clock pulses on the CP pin will serially shift data though the registers, and then out of the part on the Q7 and (Q7not) pins. The DS pin feeds into the first register and can be used to connect multiple HC165 parts together in a longer chain.

[mackrackit]

I think I see some of the problem, sorry I missed it earlier.

ANSELH = 0
should be
ANSEL = 0

And I just tried this on my simulator (bread board) to see if anything else was missing.

Change the PIC ports to match your setup.


'74HC165 CONNECTIONS
'VSS = PIN #8 AND PIN# 15
'VDD = PIN #16
'No Connect = PIN #9 AND PIN# 10
Clock VAR PORTF.6 'PIN #2 74HC165
Load VAR PORTF.7 'PIN #1 74HC165
Data_1 VAR PORTF.5 'PIN #7 74HC165
KEYS VAR BYTE
HIGH Load

READ_KEYS:
PULSOUT Load,1
SHIFTIN Data_1,Clock,0,[KEYS]
PAUSE 100
LCDOUT $FE,1,"KEYS= ",BIN8 KEYS
GOTO READ_KEYS

[lerameur]

that might be just it:
From the datasheet:
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.

But it also says the same for ANSELH, should I but both of them to 0 ??

[mackrackit]

ANSELH is for ports AN8 to AN13, and comparators.
The only register associated with PORTE are ANSEL, PORTE, and TRISE.

[lerameur]

Yep your right, its working fine now, thanks a million bits.