trouble with clamp diodes

[dsicon]

I am having the following problem and am looking for advice on the internal structure of the clamp diodes:

chip = PIC18LF2520, pins at issue, RB0, RB1, set as inputs

i have driving sources from a 74hc logic chip powered by +5V, the PIC is powered from 3.3V, so
i put 10K series resistors in line with each output from the logic gate to allow the on board clamp diodes in the PIC to clip the 5V logic high level (one logic gate output feeds RB0 through a 10K, another logic gate output feeds RB1 though 10K)

i have done this sort of thing many times with different projects and different parts

let's call the logic gate outputs Q0 & Q1

here is the issue:
when Q0 & Q1 are both low, the voltage at RB0 & RB1 is 0V as it should be (this also demonstrates that internal pullups are NOT enabled in the PIC)
when Q0 is high and Q1 is low, RB0 is ~3.8V (as expected)
BUT RB1 is at about 0.9V, which is not expected and is obviously a bad logic low level for the TTL level input requirement at the PIC

so apparently there is some sneak path through the clamping diodes that is pulling up on RB1 even though it's driving source is low?

now it gets a little more puzzling, if i lower the series resistance from 10K to 1K the circuit works much better and the .9V drops to a working low voltage level
now this is counter intuitive since the clamping current is much higher the sneak path should be worse, but i guess the same sort of path is acting on the low side and pulling it down

i will next go to 30K resistors to see what happens but i don't want to do this empirically, i really need to understand the underlying mechanisms here

can anyone please shed some light on this ?

[dsicon]

I am having the following problem and am looking for advice on the internal structure of the clamp diodes:

chip = PIC18LF2520, pins at issue, RB0, RB1, set as inputs

i have driving sources from a 74hc logic chip powered by +5V, the PIC is powered from 3.3V, so
i put 10K series resistors in line with each output from the logic gate to allow the on board clamp diodes in the PIC to clip the 5V logic high level (one logic gate output feeds RB0 through a 10K, another logic gate output feeds RB1 though 10K)

i have done this sort of thing many times with different projects and different parts

let's call the logic gate outputs Q0 & Q1

here is the issue:
when Q0 & Q1 are both low, the voltage at RB0 & RB1 is 0V as it should be (this also demonstrates that internal pullups are NOT enabled in the PIC)
when Q0 is high and Q1 is low, RB0 is ~3.8V (as expected)
BUT RB1 is at about 0.9V, which is not expected and is obviously a bad logic low level for the TTL level input requirement at the PIC

so apparently there is some sneak path through the clamping diodes that is pulling up on RB1 even though it's driving source is low?

now it gets a little more puzzling, if i lower the series resistance from 10K to 1K the circuit works much better and the .9V drops to a working low voltage level
now this is counter intuitive since the clamping current is much higher the sneak path should be worse, but i guess the same sort of path is acting on the low side and pulling it down

i will next go to 30K resistors to see what happens but i don't want to do this empirically, i really need to understand the underlying mechanisms here

can anyone please shed some light on this ?

the 30K resistors were worse, finally put diodes parallel to the r's to make good low levels

still wondering why