Clear Command stops 18F4525 dead

[khufumen]

I'm having a strange reaction with the clear command. The following simple code does not work.
The system just hangs.

OSCCON = %01110001 'Int CLK 8MHz
ADCON1 = 15 ' all digital
DEFINE OSC 8 '8MHz

p_DebugTx Var PORTB.5
Baud96YesIvn CON 16468
I var word

Clear
I = 0
MainLoop:
I = I + 1
Pause 1000
SERout2 p_DebugTx, Baud96YesIvn, [dec I, 13, 10]
Goto MainLoop

If I take out the clear command, the code works fine.
The clear command has always worked for me when using the 18F458 chips but it just doesn't want
to work on this 18F4525 chip. Any thoughts on the matter would be greatly appreciated.

Kind Regards,
Eric

[Bruce]

Does it work if you change OSCCON = %01110001 to OSCCON = %01110000?

P.S. Assuming you have an older version of PBP, you might be missing a BANK15 declaration in
18F4525.BAS.

Open 18F4525.BAS and make sure it has BANK15 $0F00, $0F7F just after BANK14 $0E00, $0EFF.

[khufumen]

Bruce,
I checked the bas file and it has the line of code in it that you thought might be missing. I'm running
the lastest PicBasicPro with the Long variable capabilities. I took out the 18F4525 and replaced it
with an 18F458 and everything runs fine. This should eliminate the possibility that it was the board I'm
using. I noticed that the 18F4525 cannot make use of the DEBUG command. Maybe there is
something else in the 18F4525 that doesn't like the CLEAR command. hmmm..........

[Bruce]

Comment out DEBUG EQU H'0FD4' in the P18F4525.INC file. Then you can use DEBUG.

[khufumen]

Eliminating that Debug issue works great! Thanks... It was a pain writing all those SEROUT2
commands. I'm just going to ignore the Clear command issue I'm having and just zero out my
variables manually. I tried using an an 8Mhz external oscillator as opposed to the internal one I was
using in the code above and I still got a problem with the clear command.

[Bruce]

CLEAR should still work! What are your config settings when using the 18F4525?

[khufumen]

Configuration commands I am using are:

Oscillator = INTRC (INTIO2)
Fail Safe Clock Monitor = Disabled
Internal External Switchover = Disabled
The configuration settings I am using are:

Powerup Timer = Disabled
Browout Reset = Enabled, SBOREN Disabled
Brownout Reset Voltage = 4.2V
Watchdog Timer = Enabled
Watchdog Timer Postscaler = 1:2
CPP2 Multiplexed with B3
PORT B Reset State = Digital I/O
Low Power Timer1 Oscillator = Higher Power
MCLR Pin Function = Input Pin
Stack Overflow / Underflow Reset = Enabled
Low Voltage Programming = Disabled
Enhanced CPU = Disabled

[Bruce]

See if CLEAR works with the watchdog timer disabled. With a WDT postscaler of 1:2 and a WDT timeout period of 4mS x the postscaler, you only have ~8mS before the WDT times-out and causes a reset.

The CLEAR macro doesn't have clrwdt instructions, and it takes ~9.91mS to clear all RAM in this part, so it resets before it has time to clear RAM. You can also bump-up the postscaler to something > 10mS, and it should work.